wip GL sim
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 737db20..5f45b14 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -66,18 +66,17 @@
rapcores rapcores0 (
-`ifndef SIM
+
`ifdef USE_POWER_PINS
- .vdda1(vdda1), // User area 1 3.3V power
- .vdda2(vdda2), // User area 2 3.3V power
- .vssa1(vssa1), // User area 1 analog ground
- .vssa2(vssa2), // User area 2 analog ground
+ //.vdda1(vdda1), // User area 1 3.3V power
+ //.vdda2(vdda2), // User area 2 3.3V power
+ //.vssa1(vssa1), // User area 1 analog ground
+ //.vssa2(vssa2), // User area 2 analog ground
.vccd1(vccd1), // User area 1 1.8V power
- .vccd2(vccd2), // User area 2 1.8V power
+ //.vccd2(vccd2), // User area 2 1.8V power
.vssd1(vssd1), // User area 1 digital ground
- .vssd2(vssd2), // User area 2 digital ground
+ //.vssd2(vssd2), // User area 2 digital ground
`endif
-`endif
// MGMT core clock and reset
.wb_clk_i(wb_clk_i),
