wip GL sim
diff --git a/verilog/dv/caravel/rapcore/io_ports/Makefile b/verilog/dv/caravel/rapcore/io_ports/Makefile
index d07edeb..e90264d 100644
--- a/verilog/dv/caravel/rapcore/io_ports/Makefile
+++ b/verilog/dv/caravel/rapcore/io_ports/Makefile
@@ -14,7 +14,7 @@
GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=$(PDK_ROOT)/sky130A
-SIM?=RTL
+SIM?=GL
.SUFFIXES:
@@ -40,7 +40,7 @@
%.vcd: %.vvp
- vvp $<
+ vvp $< -fst
%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
diff --git a/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v b/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v
index 163af61..3100231 100644
--- a/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v
@@ -45,6 +45,7 @@
wire [7:0] mprj_io_0;
assign mprj_io_0 = mprj_io[7:0];
+ assign mprj_io[3] = 1'b1;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -73,18 +74,18 @@
initial begin
// Observe Output pins [7:0]
- wait(mprj_io_0 == 8'h01);
- wait(mprj_io_0 == 8'h02);
- wait(mprj_io_0 == 8'h03);
- wait(mprj_io_0 == 8'h04);
- wait(mprj_io_0 == 8'h05);
- wait(mprj_io_0 == 8'h06);
- wait(mprj_io_0 == 8'h07);
- wait(mprj_io_0 == 8'h08);
- wait(mprj_io_0 == 8'h09);
- wait(mprj_io_0 == 8'h0A);
- wait(mprj_io_0 == 8'hFF);
- wait(mprj_io_0 == 8'h00);
+ wait(mprj_io_0 == 8'h01);
+ wait(mprj_io_0 == 8'h02);
+ wait(mprj_io_0 == 8'h03);
+ wait(mprj_io_0 == 8'h04);
+ wait(mprj_io_0 == 8'h05);
+ wait(mprj_io_0 == 8'h06);
+ wait(mprj_io_0 == 8'h07);
+ wait(mprj_io_0 == 8'h08);
+ wait(mprj_io_0 == 8'h09);
+ wait(mprj_io_0 == 8'h0A);
+ wait(mprj_io_0 == 8'hFF);
+ wait(mprj_io_0 == 8'h00);
$display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
$finish;
@@ -96,19 +97,19 @@
RSTB <= 1'b1; // Release reset
end
+ reg bootdone = 1'b0;
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
power3 <= 1'b0;
power4 <= 1'b0;
- #200;
+ #400
power1 <= 1'b1;
- #200;
power2 <= 1'b1;
- #200;
power3 <= 1'b1;
- #200;
power4 <= 1'b1;
+ #400000;
+ bootdone <= 1'b1;
end
always @(mprj_io) begin
@@ -168,7 +169,7 @@
.DIRINPUT(mprj_io[33]),
.ENINPUT(mprj_io[11]),
.ENOUTPUT(mprj_io[10]),
- .BOOT_DONE_IN(mprj_io[15])
+ .BOOT_DONE_IN(bootdone)
);
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index fa85ee2..00a9fb3 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -516,7 +516,7 @@
/* Wrapper module around the user project */
/*----------------------------------------------*/
- user_project_wrapper mprj (
+ user_project_wrapper mprj (
`ifdef USE_POWER_PINS
.vdda1(vdda1), // User area 1 3.3V power
.vdda2(vdda2), // User area 2 3.3V power
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 737db20..5f45b14 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -66,18 +66,17 @@
rapcores rapcores0 (
-`ifndef SIM
+
`ifdef USE_POWER_PINS
- .vdda1(vdda1), // User area 1 3.3V power
- .vdda2(vdda2), // User area 2 3.3V power
- .vssa1(vssa1), // User area 1 analog ground
- .vssa2(vssa2), // User area 2 analog ground
+ //.vdda1(vdda1), // User area 1 3.3V power
+ //.vdda2(vdda2), // User area 2 3.3V power
+ //.vssa1(vssa1), // User area 1 analog ground
+ //.vssa2(vssa2), // User area 2 analog ground
.vccd1(vccd1), // User area 1 1.8V power
- .vccd2(vccd2), // User area 2 1.8V power
+ //.vccd2(vccd2), // User area 2 1.8V power
.vssd1(vssd1), // User area 1 digital ground
- .vssd2(vssd2), // User area 2 digital ground
+ //.vssd2(vssd2), // User area 2 digital ground
`endif
-`endif
// MGMT core clock and reset
.wb_clk_i(wb_clk_i),
