move files to a new directory
diff --git a/rapcores b/rapcores index af0fa8a..ae3546c 160000 --- a/rapcores +++ b/rapcores
@@ -1 +1 @@ -Subproject commit af0fa8a9764b66a8737bf6f1ab3b89956ffd4c71 +Subproject commit ae3546c44a5a33778ffabb5ad6f252e018019805
diff --git a/verilog/dv/caravel/rapcore/io_ports/Makefile b/verilog/dv/caravel/rapcore/io_ports/Makefile new file mode 100644 index 0000000..f34a4d6 --- /dev/null +++ b/verilog/dv/caravel/rapcore/io_ports/Makefile
@@ -0,0 +1,63 @@ +PROJ_ROOT = ../../../../.. +FIRMWARE_PATH = ../.. +VERILOG_PATH = ../../../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +BEHAVIOURAL_MODELS = ../../ +RAPCORES_PATH = ../../../../../rapcores +GL_PATH = $(PROJ_ROOT)/openlane/rapcores/runs/rapcores/results/lvs/ + + + + +GCC_PATH?=//opt/riscv32/bin +GCC_PREFIX?=riscv32-unknown-elf +PDK_PATH?=$(PDK_ROOT)/sky130A + +SIM?=RTL + +.SUFFIXES: + +PATTERN = io_ports + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex +ifndef PDK_ROOT + $(error "!!! export PDK_ROOT= !!!!") +endif +ifeq ($(SIM),RTL) + iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \ + -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src -I $(RAPCORES_PATH)/testbench -I $(RAPCORES_PATH)/boards \ + -o $@ $< +else + iverilog -DPROJ_GL -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \ + -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \ + -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src -I $(RAPCORES_PATH)/testbench \ + -I $(RAPCORES_PATH)/boards -I $(GL_PATH) \ + -o $@ $< +endif + + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all
diff --git a/verilog/dv/caravel/rapcore/io_ports/io_ports.c b/verilog/dv/caravel/rapcore/io_ports/io_ports.c new file mode 100644 index 0000000..19c3652 --- /dev/null +++ b/verilog/dv/caravel/rapcore/io_ports/io_ports.c
@@ -0,0 +1,78 @@ +#include "../../defs.h" + +/* + IO Test: + - Configures MPRJ lower 8-IO pins as outputs + - Observes counter value through the MPRJ lower 8 IO pins (in the testbench) +*/ + +void main() +{ + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + // Configure lower 8-IOs as user output + // Observe counter value in the testbench + reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_7 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + // Configure LA probes [31:0], [127:64] as inputs to the cpu + // Configure LA probes [63:32] as outputs from the cpu + reg_la0_ena = 0xFFFFFFFF; // [31:0] + reg_la1_ena = 0x00000000; // [95:64] + reg_la2_ena = 0x00000000; // [63:32] + reg_la3_ena = 0xFFFFFFFF; // [127:96] + + // Set Counter value to zero through LA probes [63:32] + reg_la2_data = 0x00000003; + +}
diff --git a/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v b/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v new file mode 100644 index 0000000..57cb042 --- /dev/null +++ b/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v
@@ -0,0 +1,213 @@ +`default_nettype none + +`timescale 1 ns / 1 ps + +`include "defines.v" +`include "mpw_one_defines.v" +`include "macro_params.v" +`include "constants.v" +`include "quad_enc.v" +`include "spi.v" +`include "dda_timer.v" +`include "spi_state_machine.v" +`include "microstepper/chargepump.v" +`include "microstepper/microstepper_control.v" +`include "microstepper/mytimer_8.v" +`include "microstepper/mytimer_10.v" +`include "microstepper/microstep_counter.v" +`include "microstepper/cosine.v" +`include "microstepper/analog_out.v" +`include "microstepper/microstepper_top.v" +`include "rapcore.v" +`include "hbridge_coil.v" +`include "pwm_duty.v" +`include "rapcore_harness_tb.v" + +//`define USE_POWER_PINS + +`ifdef PROJ_GL + `include "rapcores.lvs.powered.v" +`else + `include "rapcores.v" +`endif + +`include "caravel.v" +`include "spiflash.v" + +module io_ports_tb; + reg clock; + reg RSTB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + + assign mprj_io_0 = mprj_io[7:0]; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + initial begin + $dumpfile("io_ports.vcd"); + $dumpvars(0, io_ports_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (25) begin + repeat (4000) @(posedge clock); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); + $display("%c[0m",27); + $finish; + end + + initial begin + // Observe Output pins [7:0] + wait(mprj_io_0 == 8'h01); + wait(mprj_io_0 == 8'h02); + wait(mprj_io_0 == 8'h03); + wait(mprj_io_0 == 8'h04); + wait(mprj_io_0 == 8'h05); + wait(mprj_io_0 == 8'h06); + wait(mprj_io_0 == 8'h07); + wait(mprj_io_0 == 8'h08); + wait(mprj_io_0 == 8'h09); + wait(mprj_io_0 == 8'h0A); + wait(mprj_io_0 == 8'hFF); + wait(mprj_io_0 == 8'h00); + + $display("Monitor: Test 1 Mega-Project IO (RTL) Passed"); + $finish; + end + + initial begin + RSTB <= 1'b0; + #2000; + RSTB <= 1'b1; // Release reset + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + #200; + power3 <= 1'b1; + #200; + power4 <= 1'b1; + end + + always @(mprj_io) begin + #1 $display("MPRJ-IO state = %b ", mprj_io[37:0]); + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3 = power1; + wire VDD1V8 = power2; + wire USER_VDD3V3 = power3; + wire USER_VDD1V8 = power4; + wire VSS = 1'b0; + + + reg step; + reg dir; + reg enable_in; + wire [12:0] target_current1; + wire [12:0] target_current2; + wire signed [12:0] current1; + wire signed [12:0] current2; + + //assign resetn = RSTB; + + rapcore_harness harness0 ( + .CLK(clock), + //.resetn_in(resetn), + .CHARGEPUMP(mprj_io[15]), + .analog_cmp1(mprj_io[25]), + .analog_out1(mprj_io[27]), + .analog_cmp2(mprj_io[26]), + .analog_out2(mprj_io[28]), + .PHASE_A1(mprj_io[23]), + .PHASE_A2(mprj_io[19]), + .PHASE_B1(mprj_io[16]), + .PHASE_B2(mprj_io[20]), + .PHASE_A1_H(mprj_io[21]), + .PHASE_A2_H(mprj_io[18]), + .PHASE_B1_H(mprj_io[14]), + .PHASE_B2_H(mprj_io[17]), + .ENC_B(mprj_io[12]), + .ENC_A(mprj_io[13]), + .BUFFER_DTR(mprj_io[37]), + .MOVE_DONE(mprj_io[24]), + .HALT(mprj_io[29]), + .SCK(mprj_io[35]), + .CS(mprj_io[34]), + .COPI(mprj_io[22]), + .CIPO(mprj_io[36]), + .STEPOUTPUT(mprj_io[30]), + .DIROUTPUT(mprj_io[31]), + .STEPINPUT(mprj_io[32]), + .DIRINPUT(mprj_io[33]), + .ENINPUT(mprj_io[11]), + .ENOUTPUT(mprj_io[10]), + .BOOT_DONE_IN(mprj_io[15]) + + ); + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + + spiflash #( + .FILENAME("io_ports.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule +`default_nettype wire