tb wip

verilog/dv/caravel/user_proj_example/io_ports/Makefile

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
index 8237f6f..aee9b64 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile
+++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
@@ -1,9 +1,11 @@
+PROJ_ROOT = ../../../../..
 FIRMWARE_PATH = ../..
 VERILOG_PATH = ../../../..
 RTL_PATH = ../../../../rtl
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../
 RAPCORES_PATH = ../../../../../rapcores
+GL_PATH = $(PROJ_ROOT)/openlane/rapcores/runs/rapcores/results/lvs/
 
 GCC_PATH?=//opt/riscv32/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -26,7 +28,9 @@
 	-o $@ $<
 else
 	iverilog -DPROJ_GL -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	-I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src  -I $(RAPCORES_PATH)/testbench \
+	-I $(RAPCORES_PATH)/boards -I $(GL_PATH) \
 	-o $@ $<
 endif
 

verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index 79aaa81..564a973 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -26,7 +26,7 @@
 //`define USE_POWER_PINS
 
 `ifdef PROJ_GL
-  `include "gl/rapcore.v"
+  `include "rapcores.lvs.powered.v"
 `else
   `include "rapcores.v"
 `endif