DRC=0 configs
diff --git a/openlane/rapcore/config.tcl b/openlane/rapcore/config.tcl index 4cafc01..e0d8c8c 100644 --- a/openlane/rapcore/config.tcl +++ b/openlane/rapcore/config.tcl
@@ -27,7 +27,7 @@ set ::env(CLOCK_PERIOD) "15" set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 540 540" +set ::env(DIE_AREA) "0 0 650 650" # use the empty wrapper to help pin placement set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg @@ -36,14 +36,14 @@ # Some config for hardening set ::env(DESIGN_IS_CORE) 0 -set ::env(GLB_RT_MAXLAYER) 5 +set ::env(GLB_RT_MAXLAYER) 4 # Diodes to fix violations set ::env(DIODE_INSERTION_STRATEGY) 3 # We try to set the die size instead #set ::env(PL_BASIC_PLACEMENT) 40 -#set ::env(PL_TARGET_DENSITY) 0.45 +set ::env(PL_TARGET_DENSITY) 0.41 # Routing # ------- @@ -55,8 +55,11 @@ # block met5 with obstruction set ::env(GLB_RT_OBS) "met5 0 0 800 800" -set ::env(VDD_PIN) vccd1 -set ::env(GND_PIN) vssd1 - +#set ::env(VDD_PIN) vccd1 +#set ::env(GND_PIN) vssd1 +set ::env(FP_PDN_VOFFSET) "14" +set ::env(FP_PDN_VPITCH) "180" +set ::env(FP_PDN_HOFFSET) "14" +set ::env(FP_PDN_HPITCH) "180"
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl index 6e49fff..0552da8 100644 --- a/openlane/user_project_wrapper/interactive.tcl +++ b/openlane/user_project_wrapper/interactive.tcl
@@ -14,7 +14,7 @@ #apply_def_template -add_macro_placement rapcore 1150 1700 N +add_macro_placement rapcore 1151 1700 N manual_macro_placement f
diff --git a/openlane/user_project_wrapper/pdn.tcl b/openlane/user_project_wrapper/pdn.tcl index 7bad0ad..dc439ff 100644 --- a/openlane/user_project_wrapper/pdn.tcl +++ b/openlane/user_project_wrapper/pdn.tcl
@@ -4,13 +4,13 @@ pdngen::specify_grid stdcell { name grid - blockages "li1 met1 met2 met3 met4" core_ring { met5 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_H_OFFSET)} met4 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_V_OFFSET)} } rails { } + blockages "li1 met1 met2 met3 met4" straps { met4 {width $::env(_WIDTH) pitch $::env(_V_PITCH) offset $::env(_V_PDN_OFFSET)} met5 {width $::env(_WIDTH) pitch $::env(_H_PITCH) offset $::env(_H_PDN_OFFSET)} @@ -38,7 +38,7 @@ connect {} } -set ::halo 10 +set ::halo 0 # POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area set ::rails_start_with "POWER" ;