| The qflow directory entries are only used to verify the all-digital frequency |
| locked loop circuit by running the verilog modules ring_osc2x13 and |
| digital_pll_controller seperately through synthesis. |
| |
| The ring_osc2x13 module is all gate-level except for a small amount of trivial |
| glue logic, so the fact that it is synthesized in qflow instead of openlane |
| (with a different setup passed to yosys) does not change the core part of the |
| ring oscillator that needs to be simulated. The synthesis results in a SPICE |
| netlist that can be simulated. |
| |
| For the digital_pll_controller, it is only needed to have a functional xspice |
| circuit of the digital part that can be used in the ngspice simulation. |
| |
| See the caravel/ngspice/digital_pll directory for the ngspice simulations. |
| |
| None of the files in this tree are used for the actual synthesis, placement, |
| and routing. The source files for qflow are pointers back to the verilog |
| module files in caravel/verilog/rtl/ directory. |
| |
| Qflow was only run through the "synthesis" stage to obtain the necessary |
| netlists. These can be recreated on demand from qflow, so the required |
| netlists were copied back to caravel/ngspice/digital_pll and the qflow |
| directory cleaned out. |
| |
| To reproduce the results, it is necessary to have the "tech" directory as a |
| symbolic link pointing to the open_pdks installation of sky130A. |
