first pass io_tb

verilog/dv/caravel/user_proj_example/io_ports/io_ports.c

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
index f6a829d..ace6004 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
@@ -34,6 +34,30 @@
 	reg_mprj_io_5 =  GPIO_MODE_USER_STD_OUTPUT;
 	reg_mprj_io_6 =  GPIO_MODE_USER_STD_OUTPUT;
 	reg_mprj_io_7 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_14 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_15 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_16 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_17 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_18 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
+	reg_mprj_io_19 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
+	reg_mprj_io_20 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_21 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_22 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
+	reg_mprj_io_23 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_24 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_25 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
+	reg_mprj_io_26 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
+	reg_mprj_io_27 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_28 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_29 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
+	reg_mprj_io_30 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_31 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_32 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
+	reg_mprj_io_33 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
+	reg_mprj_io_34 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
+	reg_mprj_io_35 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
+	reg_mprj_io_36 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_37 =  GPIO_MODE_USER_STD_OUTPUT;
 
         /* Apply configuration */
         reg_mprj_xfer = 1;

verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index bbc2390..3400011 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -19,6 +19,8 @@
 `include "microstepper/analog_out.v"
 `include "microstepper/microstepper_top.v"
 `include "rapcore.v"
+`include "hbridge_coil.v"
+`include "pwm_duty.v"
 
 //`define USE_POWER_PINS
 
@@ -148,6 +150,34 @@
 		.resetb	  (RSTB)
 	);
 
+
+    reg                 step;
+    reg                 dir;
+    reg                 enable_in;
+    wire        [12:0]  target_current1;
+    wire        [12:0]  target_current2;
+    wire signed  [12:0]  current1;
+    wire signed  [12:0]  current2;
+
+	wire analog_out1;
+	wire analog_out2;
+    reg             analog_cmp1;
+    reg             analog_cmp2;
+    reg     [40:0]  step_clock;
+    reg     [20:0]  cnt;
+    reg     [12:0]  current_abs1;
+    reg     [12:0]  current_abs2;
+    wire            phase_a1_l;
+    wire            phase_a2_l;
+    wire            phase_b1_l;
+    wire            phase_b2_l;
+    wire            phase_a1_h;
+    wire            phase_a2_h;
+    wire            phase_b1_h;
+    wire            phase_b2_h;
+	wire 			resetn;
+
+
 	spiflash #(
 		.FILENAME("io_ports.hex")
 	) spiflash (
@@ -159,5 +189,101 @@
 		.io3()			// not used
 	);
 
+//	assign CHARGEPUMP		= mprj_io[15];
+	assign analog_out1		= mprj_io[27];
+	assign analog_out2		= mprj_io[28];
+	assign phase_a1_l			= mprj_io[23];
+	assign phase_a2_l			= mprj_io[19];
+	assign phase_b1_l			= mprj_io[16];
+	assign phase_b2_l			= mprj_io[20];
+	assign phase_a1_h		= mprj_io[21];
+	assign phase_a2_h		= mprj_io[18];
+	assign phase_b1_h		= mprj_io[14];
+	assign phase_b2_h		= mprj_io[17];
+//	assign BUFFER_DTR		= mprj_io[37];
+//	assign MOVE_DONE		= mprj_io[24];
+//	assign CIPO				= mprj_io[36];
+//	assign STEPOUTPUT		= mprj_io[30];
+//	assign DIROUTPUT		= mprj_io[31];
+	assign mprj_io[25]		= analog_cmp1;
+	assign mprj_io[26]		= analog_cmp2;
+//	assign mprj_io[18]		= ENC_B;
+//	assign mprj_io[19]		= ENC_A;
+//	assign mprj_io[29]		= HALT;
+//	assign mprj_io[35]		= SCK;
+//	assign mprj_io[34]		= CS;
+//	assign mprj_io[22]		= COPI;
+	assign mprj_io[32]		= step;
+	assign mprj_io[33]		= dir;
+	assign resetn = ~RSTB;
+
+    always @(posedge clock) begin
+        if (!resetn) begin
+            cnt <= 0;
+            analog_cmp1 <= 1;
+            analog_cmp2 <= 1;
+            step <= 1;
+            step_clock = 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            enable_in <= 1;
+            if (current1[12] == 1'b1) begin
+                current_abs1 = -current1;
+            end
+            else begin
+                current_abs1 = current1;
+            end
+            if (current2[12] == 1'b1) begin
+                current_abs2 = -current2;
+            end
+            else begin
+                current_abs2 = current2;
+            end
+            step_clock <= step_clock + 1;
+            step <= step_clock[10];
+            analog_cmp1 <= (current_abs1[11:0] >= target_current1[11:0]); // compare unsigned
+            analog_cmp2 <= (current_abs2[11:0] >= target_current2[11:0]);
+            if (cnt <= 20'h4CA9) begin
+                dir <= 1;
+            end
+            else
+                dir <= 0;
+        end
+    end
+
+    pwm_duty duty1(
+        .clk(clock),
+        .resetn(resetn),
+        .pwm(analog_out1),
+        .duty(target_current1)
+    );
+    pwm_duty duty2(
+        .clk(clock),
+        .resetn(resetn),
+        .pwm(analog_out2),
+        .duty(target_current2)
+    );
+    hbridge_coil hbridge_coil1(
+        .clk(clock),
+        .resetn(resetn),
+        .low_1(phase_a1_l),
+        .high_1(phase_a1_h),
+        .low_2(phase_a2_l),
+        .high_2(phase_a2_h),
+        .current(current1),
+        .polarity_invert_config(1'b0)
+    );
+    hbridge_coil hbridge_coil2(
+        .clk(clock),
+        .resetn(resetn),
+        .low_1(phase_b1_l),
+        .high_1(phase_b1_h),
+        .low_2(phase_b2_l),
+        .high_2(phase_b2_h),
+        .current(current2),
+        .polarity_invert_config(1'b0)
+    );
 endmodule
 `default_nettype wire
+