io_tb gl experiments
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile index 208084d..e19cd5e 100644 --- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile +++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
@@ -21,12 +21,14 @@ %.vvp: %_tb.v %.hex ifeq ($(SIM),RTL) iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \ - -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src -I $(RAPCORES_PATH)/testbench \ + -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src \ + -I $(RAPCORES_PATH)/testbench -I $(RAPCORES_PATH)/boards \ -o $@ $< else - iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) -I $(RAPCORES_PATH)/boards \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src \ - -o $@ $< + -I $(RAPCORES_PATH)/testbench \ + $< -o $@ endif # MERGE: -I $(VERILOG_PATH) maybe needed for GL
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v index 579ad1d..ad1ddee 100644 --- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v +++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -2,32 +2,31 @@ `timescale 1 ns / 1 ps -`include "defines.v" -`include "rapcore_caravel_defines.v" -`include "macro_params.v" -`include "constants.v" -`include "quad_enc.v" -`include "spi.v" -`include "dda_timer.v" -`include "spi_state_machine.v" -`include "microstepper/chargepump.v" -`include "microstepper/microstepper_control.v" -`include "microstepper/mytimer_8.v" -`include "microstepper/mytimer_10.v" -`include "microstepper/microstep_counter.v" -`include "microstepper/cosine.v" -`include "microstepper/analog_out.v" -`include "microstepper/microstepper_top.v" -`include "rapcore.v" -`include "hbridge_coil.v" -`include "pwm_duty.v" - //`define USE_POWER_PINS -`ifdef PROJ_GL +`ifdef GL `include "gl/rapcore.v" `else `include "rapcores.v" + `include "defines.v" + `include "mpw_one_defines.v" + `include "macro_params.v" + `include "constants.v" + `include "quad_enc.v" + `include "spi.v" + `include "dda_timer.v" + `include "spi_state_machine.v" + `include "microstepper/chargepump.v" + `include "microstepper/microstepper_control.v" + `include "microstepper/mytimer_8.v" + `include "microstepper/mytimer_10.v" + `include "microstepper/microstep_counter.v" + `include "microstepper/cosine.v" + `include "microstepper/analog_out.v" + `include "microstepper/microstepper_top.v" + `include "rapcore.v" + `include "hbridge_coil.v" + `include "pwm_duty.v" `endif `include "caravel.v" @@ -207,7 +206,7 @@ step <= step_clock[10]; analog_cmp1 <= (current_abs1[11:0] >= target_current1[11:0]); // compare unsigned analog_cmp2 <= (current_abs2[11:0] >= target_current2[11:0]); - if (cnt <= 20'h4CA9) begin + if (cnt <= 20'hC400) begin dir <= 1; end else