0 LVS errors on rapcores 2035c297d using proj_example variant as a top layer abstraction for rapcore
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index fb0b56c..c9c962b 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -64,70 +64,46 @@
/* User project is instantiated here */
/*--------------------------------------*/
- rapcore rapcore (
+ rapcores rapcores0 (
+ `ifdef USE_POWER_PINS
+ .vdda1(vdda1), // User area 1 3.3V power
+ .vdda2(vdda2), // User area 2 3.3V power
+ .vssa1(vssa1), // User area 1 analog ground
+ .vssa2(vssa2), // User area 2 analog ground
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vccd2(vccd2), // User area 2 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+ .vssd2(vssd2), // User area 2 digital ground
+ `endif
- // IO Pads
- .CLK(wb_clk_i),
- .CHARGEPUMP(io_out[15]),
- .analog_cmp1(io_in[25]),
- .analog_out1(io_out[27]),
- .analog_cmp2(io_in[26]),
- .analog_out2(io_out[28]),
- .PHASE_A1(io_out[23]),
- .PHASE_A2(io_out[19]),
- .PHASE_B1(io_out[16]),
- .PHASE_B2(io_out[20]),
- .PHASE_A1_H(io_out[21]),
- .PHASE_A2_H(io_out[18]),
- .PHASE_B1_H(io_out[14]),
- .PHASE_B2_H(io_out[17]),
- .ENC_B(io_in[18]),
- .ENC_A(io_in[19]),
- .BUFFER_DTR(io_out[12]),
- .MOVE_DONE(io_out[24]),
- .HALT(io_in[29]),
- .SCK(io_in[10]),
- .CS(io_in[9]),
- .COPI(io_in[8]),
- .CIPO(io_out[11]),
- .STEPOUTPUT(io_out[30]),
- .DIROUTPUT(io_out[31]),
- .STEPINPUT(io_in[32]),
- .DIRINPUT(io_in[33])
+ // MGMT core clock and reset
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ // MGMT SoC Wishbone Slave
+
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer
+
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oen (la_oen),
+
+ // IO Pads
+
+ .io_in (io_in),
+ .io_out(io_out),
+ .io_oeb(io_oeb)
);
endmodule // user_project_wrapper
-
-(* blackbox *)
-module rapcore (
- input CLK,
- input SCK,
- input CS,
- input COPI,
- output CIPO,
- output CHARGEPUMP,
- input analog_cmp1,
- output analog_out1,
- input analog_cmp2,
- output analog_out2,
- output wire PHASE_A1, // Phase A
- output wire PHASE_A2, // Phase A
- output wire PHASE_B1, // Phase B
- output wire PHASE_B2, // Phase B
- output wire PHASE_A1_H, // Phase A
- output wire PHASE_A2_H, // Phase A
- output wire PHASE_B1_H, // Phase B
- output wire PHASE_B2_H, // Phase B
- input ENC_B,
- input ENC_A,
- output BUFFER_DTR,
- output MOVE_DONE,
- input HALT,
- input STEPINPUT,
- input DIRINPUT,
- output STEPOUTPUT,
- output DIROUTPUT
-);
-endmodule
-
`default_nettype wire
