verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw

[*]
[*] GTKWave Analyzer v3.3.108 (w)1999-2020 BSI
[*] Thu Nov 26 13:29:36 2020
[*]
[dumpfile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.vcd"
[dumpfile_mtime] "Thu Nov 26 13:28:55 2020"
[dumpfile_size] 194298414
[savefile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw"
[timestart] 0
[size] 1700 1529
[pos] -1 -1
*-28.000000 253000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] vga_clock_tb.
[treeopen] vga_clock_tb.uut.
[treeopen] vga_clock_tb.uut.gpio_control_bidir[0].gpio_in_buf.
[treeopen] vga_clock_tb.uut.gpio_control_in[4].gpio_in_buf.
[treeopen] vga_clock_tb.uut.gpio_control_in[4].gpio_logic_high.
[treeopen] vga_clock_tb.uut.gpio_control_in[8].
[treeopen] vga_clock_tb.uut.gpio_control_in[8].gpio_in_buf.
[treeopen] vga_clock_tb.uut.mprj.
[treeopen] vga_clock_tb.uut.mprj.mprj.
[treeopen] vga_clock_tb.uut.mprj.mprj.proj_0.
[treeopen] vga_clock_tb.uut.mprj.mprj.proj_2.
[treeopen] vga_clock_tb.uut.soc.
[treeopen] vga_clock_tb.uut.soc.housekeeping.
[treeopen] vga_clock_tb.uut.soc.soc.
[treeopen] vga_clock_tb.uut.soc.soc.cpu.
[treeopen] vga_clock_tb.uut.soc.soc.cpu.picorv32_core.
[treeopen] vga_clock_tb.uut.soc.soc.gpio_wb.
[treeopen] vga_clock_tb.uut.soc.soc.mprj_ctrl.
[sst_width] 506
[signals_width] 741
[sst_expanded] 1
[sst_vpaned_height] 862
@28
vga_clock_tb.clock
vga_clock_tb.RSTB
@200
-
@800200
-wbs
@28
vga_clock_tb.uut.mprj.mprj.wb_rst_i
vga_clock_tb.uut.mprj.mprj.wb_clk_i
vga_clock_tb.uut.mprj.mprj.wbs_ack_o
@22
vga_clock_tb.uut.mprj.mprj.wbs_adr_i[31:0]
@28
vga_clock_tb.uut.mprj.mprj.wbs_cyc_i
@24
vga_clock_tb.uut.mprj.mprj.wbs_dat_i[31:0]
@22
vga_clock_tb.uut.mprj.mprj.wbs_dat_o[31:0]
vga_clock_tb.uut.mprj.mprj.wbs_sel_i[3:0]
@28
vga_clock_tb.uut.mprj.mprj.wbs_stb_i
vga_clock_tb.uut.mprj.mprj.wbs_we_i
@1000200
-wbs
@800200
-multi proj control
@28
vga_clock_tb.uut.soc.soc.mprj_ctrl.mprj_ctrl.xfer_ctrl
@1000200
-multi proj control
@800200
-la
@22
vga_clock_tb.uut.mprj.mprj.la_data_in[127:0]
vga_clock_tb.uut.mprj.mprj.la_data_out[127:0]
vga_clock_tb.uut.mprj.mprj.la_oen[127:0]
@1000200
-la
@22
vga_clock_tb.uut.soc.soc.cpu.picorv32_core.next_insn_opcode[31:0]
@200
-
@800200
-multi project
@22
vga_clock_tb.uut.mprj.mprj.active_project[7:0]
@23
vga_clock_tb.uut.mprj.mprj.reg_oeb[37:0]
@28
vga_clock_tb.uut.mprj.mprj.wb_rst_i
@c00022
vga_clock_tb.uut.mprj.io_in[37:0]
@28
(0)vga_clock_tb.uut.mprj.io_in[37:0]
(1)vga_clock_tb.uut.mprj.io_in[37:0]
(2)vga_clock_tb.uut.mprj.io_in[37:0]
(3)vga_clock_tb.uut.mprj.io_in[37:0]
(4)vga_clock_tb.uut.mprj.io_in[37:0]
(5)vga_clock_tb.uut.mprj.io_in[37:0]
(6)vga_clock_tb.uut.mprj.io_in[37:0]
(7)vga_clock_tb.uut.mprj.io_in[37:0]
(8)vga_clock_tb.uut.mprj.io_in[37:0]
(9)vga_clock_tb.uut.mprj.io_in[37:0]
(10)vga_clock_tb.uut.mprj.io_in[37:0]
(11)vga_clock_tb.uut.mprj.io_in[37:0]
(12)vga_clock_tb.uut.mprj.io_in[37:0]
(13)vga_clock_tb.uut.mprj.io_in[37:0]
(14)vga_clock_tb.uut.mprj.io_in[37:0]
(15)vga_clock_tb.uut.mprj.io_in[37:0]
(16)vga_clock_tb.uut.mprj.io_in[37:0]
(17)vga_clock_tb.uut.mprj.io_in[37:0]
(18)vga_clock_tb.uut.mprj.io_in[37:0]
(19)vga_clock_tb.uut.mprj.io_in[37:0]
(20)vga_clock_tb.uut.mprj.io_in[37:0]
(21)vga_clock_tb.uut.mprj.io_in[37:0]
(22)vga_clock_tb.uut.mprj.io_in[37:0]
(23)vga_clock_tb.uut.mprj.io_in[37:0]
(24)vga_clock_tb.uut.mprj.io_in[37:0]
(25)vga_clock_tb.uut.mprj.io_in[37:0]
(26)vga_clock_tb.uut.mprj.io_in[37:0]
(27)vga_clock_tb.uut.mprj.io_in[37:0]
(28)vga_clock_tb.uut.mprj.io_in[37:0]
(29)vga_clock_tb.uut.mprj.io_in[37:0]
(30)vga_clock_tb.uut.mprj.io_in[37:0]
(31)vga_clock_tb.uut.mprj.io_in[37:0]
(32)vga_clock_tb.uut.mprj.io_in[37:0]
(33)vga_clock_tb.uut.mprj.io_in[37:0]
(34)vga_clock_tb.uut.mprj.io_in[37:0]
(35)vga_clock_tb.uut.mprj.io_in[37:0]
(36)vga_clock_tb.uut.mprj.io_in[37:0]
(37)vga_clock_tb.uut.mprj.io_in[37:0]
@1401200
-group_end
@c00022
vga_clock_tb.uut.mprj.mprj.io_out[37:0]
@28
(0)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(1)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(2)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(3)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(4)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(5)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(6)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(7)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(8)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(9)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(10)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(11)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(12)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(13)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(14)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(15)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(16)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(17)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(18)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(19)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(20)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(21)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(22)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(23)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(24)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(25)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(26)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(27)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(28)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(29)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(30)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(31)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(32)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(33)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(34)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(35)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(36)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
(37)vga_clock_tb.uut.mprj.mprj.io_out[37:0]
@1401200
-group_end
@1000200
-multi project
@28
vga_clock_tb.uut.mprj.mprj.proj_2.reset
@22
vga_clock_tb.uut.mprj.mprj.proj_2.hrs_u[3:0]
@28
vga_clock_tb.uut.mprj.mprj.proj_2.hrs_d[1:0]
vga_clock_tb.adj_hrs
vga_clock_tb.uut.gpio_control_in[8].pad_gpio_in
vga_clock_tb.uut.gpio_control_in[8].pad_gpio_in
vga_clock_tb.uut.gpio_control_in[8].pad_gpio_inenb
vga_clock_tb.uut.gpio_control_in[8].pad_gpio_outenb
vga_clock_tb.uut.mprj.mprj.proj_2.adj_hrs
vga_clock_tb.uut.mprj.mprj.proj_2.px_clk
@24
vga_clock_tb.uut.mprj.mprj.proj_2.y_px[9:0]
vga_clock_tb.uut.mprj.mprj.proj_2.x_px[9:0]
@28
vga_clock_tb.uut.mprj.mprj.proj_2.activevideo
vga_clock_tb.uut.mprj.mprj.proj_2.vsync
vga_clock_tb.hsync
@22
vga_clock_tb.rrggbb[5:0]
[pattern_trace] 1
[pattern_trace] 0