blob: 615e142a1791f3fae5b28941466e1f5b6e95544f [file] [log] [blame]
project:
category: Test Harness
cover_image: doc/ciic_harness.png
description: Peripherals tests for future SoC targeting Micro/Circuit Python
foundry: SkyWater
git_url: https://github.com/PyFive-RISC-V/caravel
layout_image: gds/caravel.png
organization: PyFive
organization_url: https://github.com/PyFive-RISC-V
owner: Michael Welling / Sylvain Munaut
process: SKY130
project_id: 0001000a
project_name: Caravel
shuttle_url: https://foss-eda-tools.googlesource.com/third_party/shuttle/sky130/mpw-001/slot-010
tags:
- Open MPW
- USB
- RISC-V
top_level_netlist: verilog/gl/caravel.v
user_level_netlist: verilog/gl/user_project_wrapper.v
version: '1.00'