update user_project_wrapper pins

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 47d92f4..1ed71a9 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -117,7 +117,9 @@
 
 	.io_in (io_in),
     	.io_out(io_out),
-    	.io_oeb(io_oeb)
+    	.io_oeb(io_oeb),
+
+        .analog_io(analog_io)
     );
 
 endmodule	// user_project_wrapper