commit f393d1e1780c7ed41f98bd1bfb492dcdded1a355
author nurirfansyah <nurirfansyah@yahoo.com> Wed Dec 02 22:02:55 2020 +0700
committer nurirfansyah <nurirfansyah@yahoo.com> Wed Dec 16 14:48:39 2020 +0700
tree 72a6490288906b9a9fecc9f93cd7708a80275d76
parent 96ada6372eb802e6f94979109213543d3d1fc7e4

update user_project_wrapper pins

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 47d92f4..1ed71a9 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -117,7 +117,9 @@
 
 	.io_in (io_in),
     	.io_out(io_out),
-    	.io_oeb(io_oeb)
+    	.io_oeb(io_oeb),
+
+        .analog_io(analog_io)
     );
 
 endmodule	// user_project_wrapper