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foss-eda-tools/third_party/shuttle/sky130/mpw-001/slot-009/a997ad90af6f57d7c36fa6ceef58b1beb38a97e9^!/.
commit
a997ad90af6f57d7c36fa6ceef58b1beb38a97e9
[log]
author
Ahmed Ghazy <ax3ghazy@aucegypt.edu>
Wed Nov 25 04:02:15 2020 +0200
committer
Ahmed Ghazy <ax3ghazy@aucegypt.edu>
Wed Nov 25 04:02:15 2020 +0200
tree
fad9bbf68081418f8404595cc6ca6fa85b25b65f
parent
e4c7ec5a4e26d485cee0a17a75f4d1758cf8481b [diff]
Update chip_io configs of the LVS clean padframe

diff --git a/openlane/chip_io/config.tcl b/openlane/chip_io/config.tcl
old mode 100644
new mode 100755
index 9a2145a..dba3bbc
--- a/openlane/chip_io/config.tcl
+++ b/openlane/chip_io/config.tcl

@@ -15,13 +15,18 @@
 set ::env(SYNTH_FLAT_TOP) 1
 set ::env(USE_GPIO_PADS) 1
 
+
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 3588 5188"
+
+set fd [open "$script_dir/../chip_dimensions.txt" "r"]
+set ::env(DIE_AREA) [read $fd]
+close $fd
 
 
 set ::env(MAGIC_WRITE_FULL_LEF) 1
 
 set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(GLB_RT_TILES) 20
+set ::env(GLB_RT_TILES) 12
 set ::env(GLB_RT_UNIDIRECTIONAL) 0
 # set ::env(GLB_RT_ALLOW_CONGESTION) 1
+# set ::env(GLB_RT_OVERFLOW_ITERS) 150

diff --git a/openlane/chip_io/interactive.tcl b/openlane/chip_io/interactive.tcl
old mode 100644
new mode 100755
index 2529819..8e5de2e
--- a/openlane/chip_io/interactive.tcl
+++ b/openlane/chip_io/interactive.tcl

@@ -1,19 +1,31 @@
 package require openlane
 set script_dir [file dirname [file normalize [info script]]]
-
-prep -design $script_dir -tag chip_io -overwrite
 set save_path $script_dir/../..
 
-# set ::env(SYNTH_DEFINES) ""
-# verilog_elaborate
-# init_floorplan
-# file copy $::env(CURRENT_DEF) $::env(TMP_DIR)/lvs.def
+# FOR LVS AND CREATING PORT LABELS
+set ::env(USE_GPIO_ROUTING_LEF) 0
+prep -design $script_dir -tag chip_io_lvs -overwrite
+
+set ::env(SYNTH_DEFINES) ""
+verilog_elaborate
+init_floorplan
+file copy -force $::env(CURRENT_DEF) $::env(TMP_DIR)/lvs.def
+file copy -force $::env(CURRENT_NETLIST) $::env(TMP_DIR)/lvs.v
+
+# ACTUAL CHIP INTEGRATION
+set ::env(USE_GPIO_ROUTING_LEF) 1
+prep -design $script_dir -tag chip_io -overwrite
+
+file copy $script_dir/runs/chip_io_lvs/tmp/merged_unpadded.lef $::env(TMP_DIR)/lvs.lef
+file copy $script_dir/runs/chip_io_lvs/tmp/lvs.def $::env(TMP_DIR)/lvs.def
+file copy $script_dir/runs/chip_io_lvs/tmp/lvs.v $::env(TMP_DIR)/lvs.v
 
 set ::env(SYNTH_DEFINES) "TOP_ROUTING"
 verilog_elaborate
 
 init_floorplan
 
+puts_info "Generating pad frame"
 exec -ignorestderr python3 $::env(SCRIPTS_DIR)/padringer.py\
 	--def-netlist $::env(CURRENT_DEF)\
 	--design $::env(DESIGN_NAME)\
@@ -21,50 +33,49 @@
 	-cfg $script_dir/padframe.cfg\
 	--working-dir $::env(TMP_DIR)\
 	-o $::env(RESULTS_DIR)/floorplan/padframe.def
+puts_info "Generated pad frame"
 
 set_def $::env(RESULTS_DIR)/floorplan/padframe.def
 
 # modify to a different file
 remove_pins -input $::env(CURRENT_DEF)
-
 remove_empty_nets -input $::env(CURRENT_DEF)
 
 add_macro_obs \
 	-defFile $::env(CURRENT_DEF) \
 	-lefFile $::env(MERGED_LEF_UNPADDED) \
 	-obstruction core_obs \
-	-placementX 500 \
-	-placementY 500 \
-	-sizeWidth 2200 \
-	-sizeHeight 4300 \
+	-placementX 230 \
+	-placementY 240 \
+	-sizeWidth 3132 \
+	-sizeHeight 4710 \
 	-fixed 1 \
 	-layerNames "met1 met2 met3 met4 met5"
 
-
 li1_hack_start
 global_routing
 detailed_routing
 li1_hack_end
 
-# label_macro_pins\
-# 	-lef $::env(MERGED_LEF_UNPADDED)\
-# 	-netlist_def $::env(CURRENT_DEF)\
-# 	-pad_pin_name "PAD"\
-# 	-extra_args {-v\
-# 	--map mgmt_vdda_hvclamp_pad VDDA vdda INOUT\
-# 	--map user1_vdda_hvclamp_pad\\\[0\\] VDDA vdda1 INOUT\
-# 	--map user2_vdda_hvclamp_pad VDDA vdda2 INOUT\
-# 	--map mgmt_vssa_hvclamp_pad VSSA vssa INOUT\
-# 	--map user1_vssa_hvclamp_pad\\\[0\\] VSSA vssa1 INOUT\
-# 	--map user2_vssa_hvclamp_pad VSSA vssa2 INOUT\
-# 	--map mgmt_vccd_lvclamp_pad VCCD vccd INOUT\
-# 	--map user1_vccd_lvclamp_pad VCCD vccd1 INOUT\
-# 	--map user2_vccd_lvclamp_pad VCCD vccd2 INOUT\
-# 	--map mgmt_vssd_lvclmap_pad VSSD vssd INOUT\
-# 	--map user1_vssd_lvclmap_pad VSSD vssd1 INOUT\
-# 	--map user2_vssd_lvclmap_pad VSSD vssd2 INOUT\
-# 	--map mgmt_vddio_hvclamp_pad\\\[0\\] VDDIO vddio INOUT\
-# 	--map mgmt_vssio_hvclamp_pad\\\[0\\] VSSIO vssio INOUT}
+label_macro_pins\
+	-lef $::env(TMP_DIR)/lvs.lef\
+	-netlist_def $::env(TMP_DIR)/lvs.def\
+	-pad_pin_name "PAD"\
+	-extra_args {-v\
+	--map mgmt_vdda_hvclamp_pad VDDA vdda INOUT\
+	--map user1_vdda_hvclamp_pad\\\[0\\] VDDA vdda1 INOUT\
+	--map user2_vdda_hvclamp_pad VDDA vdda2 INOUT\
+	--map mgmt_vssa_hvclamp_pad VSSA vssa INOUT\
+	--map user1_vssa_hvclamp_pad\\\[0\\] VSSA vssa1 INOUT\
+	--map user2_vssa_hvclamp_pad VSSA vssa2 INOUT\
+	--map mgmt_vccd_lvclamp_pad VCCD vccd INOUT\
+	--map user1_vccd_lvclamp_pad VCCD vccd1 INOUT\
+	--map user2_vccd_lvclamp_pad VCCD vccd2 INOUT\
+	--map mgmt_vssd_lvclmap_pad VSSD vssd INOUT\
+	--map user1_vssd_lvclmap_pad VSSD vssd1 INOUT\
+	--map user2_vssd_lvclmap_pad VSSD vssd2 INOUT\
+	--map mgmt_vddio_hvclamp_pad\\\[0\\] VDDIO vddio INOUT\
+	--map mgmt_vssio_hvclamp_pad\\\[0\\] VSSIO vssio INOUT}
 
 
 run_magic
@@ -79,5 +90,5 @@
                  -tag $::env(RUN_TAG)
 
 
-# run_magic_spice_export
-# run_lvs
+run_magic_spice_export
+run_lvs $::env(magic_result_file_tag).spice $::env(TMP_DIR)/lvs.v

diff --git a/openlane/chip_io/padframe.cfg b/openlane/chip_io/padframe.cfg
index d73bd0b..fde59c2 100644
--- a/openlane/chip_io/padframe.cfg
+++ b/openlane/chip_io/padframe.cfg

@@ -1,73 +1,237 @@
-AREA 3200 5300 ;
+AREA 3588 5188 ;
 
 CORNER mgmt_corner\[0\] SW sky130_ef_io__corner_pad ;
-CORNER mgmt_corner\[1\] NW sky130_ef_io__corner_pad ;
+CORNER mgmt_corner\[1\] SE sky130_ef_io__corner_pad ;
 CORNER user1_corner NE sky130_ef_io__corner_pad ;
-CORNER user2_corner SE sky130_ef_io__corner_pad ;
+CORNER user2_corner NW sky130_ef_io__corner_pad ;
 
-PAD mprj_pads.area2_io_pad\[5\] N sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[4\] N sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[3\] N sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[2\] N sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[1\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[5\] N sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[4\] N sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[3\] N sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[2\] N sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[1\] N sky130_ef_io__gpiov2_pad_wrapped ;
 PAD mgmt_vssio_hvclamp_pad\[0\] N sky130_ef_io__vssio_hvc_pad ;
-PAD mprj_pads.area2_io_pad\[0\] N sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area1_io_pad\[17\] N sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area1_io_pad\[16\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[0\] N sky130_ef_io__gpiov2_pad_wrapped ;
+PAD disconnect_vdda_0 N sky130_ef_io__disconnect_vdda_slice_5um ;
+SPACE 0 ;
+PAD disconnect_vccd_0 N sky130_ef_io__disconnect_vccd_slice_5um ;
+PAD mprj_pads.area1_io_pad\[17\] N sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area1_io_pad\[16\] N sky130_ef_io__gpiov2_pad_wrapped ;
 PAD user1_vssa_hvclamp_pad\[0\] N sky130_ef_io__vssa_hvc_pad ;
-PAD mprj_pads.area1_io_pad\[15\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[15\] N sky130_ef_io__gpiov2_pad_wrapped ;
 
-PAD mprj_pads.area1_io_pad\[0\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area1_io_pad\[1\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area1_io_pad\[2\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area1_io_pad\[3\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area1_io_pad\[4\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area1_io_pad\[5\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area1_io_pad\[6\] E sky130_ef_io__gpiov2_pad ;
+PAD disconnect_vdda_1 E sky130_ef_io__disconnect_vdda_slice_5um ;
+SPACE 0 ;
+PAD disconnect_vccd_1 E sky130_ef_io__disconnect_vccd_slice_5um ;
+PAD mprj_pads.area1_io_pad\[0\] E sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area1_io_pad\[1\] E sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area1_io_pad\[2\] E sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area1_io_pad\[3\] E sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area1_io_pad\[4\] E sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area1_io_pad\[5\] E sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area1_io_pad\[6\] E sky130_ef_io__gpiov2_pad_wrapped ;
 PAD user1_vssa_hvclamp_pad\[1\] E sky130_ef_io__vssa_hvc_pad ;
 PAD user1_vssd_lvclmap_pad E sky130_ef_io__vssd_lvc_pad ;
 PAD user1_vdda_hvclamp_pad\[1\] E sky130_ef_io__vdda_hvc_pad ;
-PAD mprj_pads.area1_io_pad\[7\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area1_io_pad\[8\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area1_io_pad\[9\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area1_io_pad\[10\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area1_io_pad\[11\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area1_io_pad\[12\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[7\] E sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area1_io_pad\[8\] E sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area1_io_pad\[9\] E sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area1_io_pad\[10\] E sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area1_io_pad\[11\] E sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area1_io_pad\[12\] E sky130_ef_io__gpiov2_pad_wrapped ;
 PAD user1_vdda_hvclamp_pad\[0\] E sky130_ef_io__vdda_hvc_pad ;
-PAD mprj_pads.area1_io_pad\[13\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[13\] E sky130_ef_io__gpiov2_pad_wrapped ;
 PAD user1_vccd_lvclamp_pad E sky130_ef_io__vccd_lvc_pad ;
-PAD mprj_pads.area1_io_pad\[14\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[14\] E sky130_ef_io__gpiov2_pad_wrapped ;
+
+PAD bus_tie_1 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_2 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_3 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_4 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_5 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_6 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
 
 PAD mgmt_vssa_hvclamp_pad S sky130_ef_io__vssa_hvc_pad ;
+
+PAD bus_tie_7 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_8 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_9 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_10 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_11 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_12 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+
 PAD resetb_pad S sky130_fd_io__top_xres4v2 ;
-PAD clock_pad S sky130_ef_io__gpiov2_pad ;
+
+PAD bus_tie_13 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_14 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_15 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_16 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_17 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_18 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD clock_pad S sky130_ef_io__gpiov2_pad_wrapped ;
+
+PAD bus_tie_19 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_20 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_21 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_22 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_23 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_24 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
 PAD mgmt_vssd_lvclmap_pad S sky130_ef_io__vssd_lvc_pad ;
-PAD flash_csb_pad S sky130_ef_io__gpiov2_pad ;
-PAD flash_clk_pad S sky130_ef_io__gpiov2_pad ;
-PAD flash_io0_pad S sky130_ef_io__gpiov2_pad ;
-PAD flash_io1_pad S sky130_ef_io__gpiov2_pad ;
-PAD gpio_pad S sky130_ef_io__gpiov2_pad ;
+
+PAD bus_tie_25 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_26 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_27 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_28 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_29 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_30 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD flash_csb_pad S sky130_ef_io__gpiov2_pad_wrapped ;
+
+PAD bus_tie_31 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_32 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_33 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_34 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_35 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_36 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD flash_clk_pad S sky130_ef_io__gpiov2_pad_wrapped ;
+
+PAD bus_tie_37 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_38 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_39 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_40 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_41 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_42 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD flash_io0_pad S sky130_ef_io__gpiov2_pad_wrapped ;
+
+PAD bus_tie_43 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_44 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_45 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_46 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_47 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_48 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD flash_io1_pad S sky130_ef_io__gpiov2_pad_wrapped ;
+
+PAD bus_tie_49 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_50 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_51 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_52 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_53 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_54 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD gpio_pad S sky130_ef_io__gpiov2_pad_wrapped ;
+
+PAD bus_tie_55 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_56 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_57 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_58 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_59 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_60 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
 PAD mgmt_vssio_hvclamp_pad\[1\] S sky130_ef_io__vssio_hvc_pad ;
+
+PAD bus_tie_61 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_62 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_63 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_64 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_65 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_66 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
 PAD mgmt_vdda_hvclamp_pad S sky130_ef_io__vdda_hvc_pad ;
 
+PAD bus_tie_67 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_68 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_69 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_70 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_71 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_72 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
 PAD mgmt_vccd_lvclamp_pad W sky130_ef_io__vccd_lvc_pad ;
 PAD mgmt_vddio_hvclamp_pad\[0\] W sky130_ef_io__vddio_hvc_pad ;
-PAD mprj_pads.area2_io_pad\[19\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[18\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[17\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[16\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[15\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[14\] W sky130_ef_io__gpiov2_pad ;
+PAD disconnect_vdda_2 W sky130_ef_io__disconnect_vdda_slice_5um ;
+SPACE 0 ;
+PAD disconnect_vccd_2 W sky130_ef_io__disconnect_vccd_slice_5um ;
+PAD mprj_pads.area2_io_pad\[19\] W sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[18\] W sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[17\] W sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[16\] W sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[15\] W sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[14\] W sky130_ef_io__gpiov2_pad_wrapped ;
 PAD user2_vssd_lvclmap_pad W sky130_ef_io__vssd_lvc_pad ;
 PAD user2_vdda_hvclamp_pad W sky130_ef_io__vdda_hvc_pad ;
-PAD mprj_pads.area2_io_pad\[13\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[12\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[11\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[10\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[9\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[8\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads.area2_io_pad\[7\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[13\] W sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[12\] W sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[11\] W sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[10\] W sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[9\] W sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[8\] W sky130_ef_io__gpiov2_pad_wrapped ;
+PAD mprj_pads.area2_io_pad\[7\] W sky130_ef_io__gpiov2_pad_wrapped ;
 PAD user2_vssa_hvclamp_pad W sky130_ef_io__vssa_hvc_pad ;
 PAD mgmt_vddio_hvclamp_pad\[1\] W sky130_ef_io__vddio_hvc_pad ;
 PAD user2_vccd_lvclamp_pad W sky130_ef_io__vccd_lvc_pad ;
-PAD mprj_pads.area2_io_pad\[6\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[6\] W sky130_ef_io__gpiov2_pad_wrapped ;