| ,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/mgmt_core,mgmt_core,mgmt_core,1h55m11s,1.8275,18974.555403556773,37949.110807113546,23,1533.24,34676,7,6,1,0,0,0,29,32,4,2903961,455064,0.0,0.0,0.0,-22.51,0.0,0.0,0.0,0.0,-27.75,0.0,2329035856,0.0,45.32,28.77,24.67,1.17,7.19,34324,35057,3633,4366,0,0,0,34676,971,152,767,773,3998,1159,281,10888,4227,4046,75,1004,17066,77203,95273,20.0,50.0,50,2,4,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,1 |
