| Notice 0: Reading LEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged.lef |
| Notice 0: Created 13 technology layers |
| Notice 0: Created 25 technology vias |
| Notice 0: Created 440 library cells |
| Notice 0: Finished LEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged.lef |
| Notice 0: |
| Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/verilog2def_openroad.def |
| Notice 0: Design: mgmt_core |
| Notice 0: Created 794 pins. |
| Notice 0: Created 34676 components and 250504 component-terminals. |
| Notice 0: Created 35057 nets and 111794 connections. |
| Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/verilog2def_openroad.def |
| Placing the following macros: |
| {'pll': ['14360', '256399', 'N'], 'soc.soc_mem.mem.SRAM': ['1333285', '123980', 'N']} |
| Design name: mgmt_core |
| Placing pll |
| Placing soc.soc_mem.mem.SRAM |
| Successfully placed 2 instances |
