commit 06bcba35ad3aab1b944b41e4bcb6a0936b018fc9
author nurirfansyah <nurirfansyah@yahoo.com> Wed Dec 02 22:07:25 2020 +0700
committer nurirfansyah <nurirfansyah@yahoo.com> Wed Dec 16 14:48:39 2020 +0700
tree 5995e473fa6a02afa54a1100297280af6416dbd4
parent f393d1e1780c7ed41f98bd1bfb492dcdded1a355

set SYNTH_READ_BLACKBOX_LIB to 1

openlane/user_proj_example/config.tcl

diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 4e5cc61..7c53312 100644
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -16,6 +16,8 @@
 set script_dir [file dirname [file normalize [info script]]]
 
 set ::env(DESIGN_NAME) user_proj_example
+set ::env(STD_CELL_LIBRARY) sky130_fd_sc_hd
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 
 set ::env(VERILOG_FILES) "\
 	$script_dir/../../verilog/rtl/defines.v \