commit	9de7415318bb55b7f35b8b73177299f7c36f2185	[log] [tgz]
author	Kevin <kevindai02@outlook.com>	Tue Dec 22 17:41:12 2020 -0500
committer	Kevin <kevindai02@outlook.com>	Tue Dec 22 17:41:12 2020 -0500
tree	fe3300793cb2b9abfd11a9c565adf8240baeba5d
parent	032cf31720f80e65f4442d33b9791aa9775b60a4 [diff]

Updated test structures

verilog/dv/caravel/hs32_soc/test1/Makefile[Renamed from verilog/dv/caravel/hs32_soc/core1test1/Makefile - diff]
verilog/dv/caravel/hs32_soc/test1/README.md[Renamed from verilog/dv/caravel/hs32_soc/core1test1/README.md - diff]
verilog/dv/caravel/hs32_soc/test1/tb.gtkw[Renamed from verilog/dv/caravel/hs32_soc/core1test1/tb.gtkw - diff]
verilog/dv/caravel/hs32_soc/test1/test1.c[Renamed from verilog/dv/caravel/hs32_soc/core1test1/test1.c - diff]
verilog/dv/caravel/hs32_soc/test1/test1_tb.v[Renamed from verilog/dv/caravel/hs32_soc/core1test1/test1_tb.v - diff]
verilog/dv/caravel/hs32_soc/test2/Makefile[Renamed from verilog/dv/caravel/hs32_soc/core1test2/Makefile - diff]
verilog/dv/caravel/hs32_soc/test2/README.md[Renamed from verilog/dv/caravel/hs32_soc/core1test2/README.md - diff]
verilog/dv/caravel/hs32_soc/test2/tb.gtkw[Renamed from verilog/dv/caravel/hs32_soc/core1test2/tb.gtkw - diff]
verilog/dv/caravel/hs32_soc/test2/test2.c[Renamed from verilog/dv/caravel/hs32_soc/core1test2/test2.c - diff]
verilog/dv/caravel/hs32_soc/test2/test2_tb.v[Renamed from verilog/dv/caravel/hs32_soc/core1test2/test2_tb.v - diff]
verilog/dv/caravel/hs32_soc/test3/Makefile[Renamed from verilog/dv/caravel/hs32_soc/core1test3/Makefile - diff]
verilog/dv/caravel/hs32_soc/test3/README.md[Renamed from verilog/dv/caravel/hs32_soc/core1test3/README.md - diff]
verilog/dv/caravel/hs32_soc/test3/tb.gtkw[Renamed from verilog/dv/caravel/hs32_soc/core1test3/tb.gtkw - diff]
verilog/dv/caravel/hs32_soc/test3/test3.c[Renamed from verilog/dv/caravel/hs32_soc/core1test3/test3.c - diff]
verilog/dv/caravel/hs32_soc/test3/test3_tb.v[Renamed from verilog/dv/caravel/hs32_soc/core1test3/test3_tb.v - diff]
verilog/dv/caravel/hs32_soc/test4/Makefile[Renamed from verilog/dv/caravel/hs32_soc/core1test4/Makefile - diff]
verilog/dv/caravel/hs32_soc/test4/README.md[Renamed from verilog/dv/caravel/hs32_soc/core1test4/README.md - diff]
verilog/dv/caravel/hs32_soc/test4/tb.gtkw[Renamed from verilog/dv/caravel/hs32_soc/core1test4/tb.gtkw - diff]
verilog/dv/caravel/hs32_soc/test4/test4.c[Renamed from verilog/dv/caravel/hs32_soc/core1test4/test4.c - diff]
verilog/dv/caravel/hs32_soc/test4/test4_tb.v[Renamed from verilog/dv/caravel/hs32_soc/core1test4/test4_tb.v - diff]
verilog/dv/caravel/hs32_soc/test5/Makefile[Renamed from verilog/dv/caravel/hs32_soc/core1test5/Makefile - diff]
verilog/dv/caravel/hs32_soc/test5/README.md[Renamed from verilog/dv/caravel/hs32_soc/core1test5/README.md - diff]
verilog/dv/caravel/hs32_soc/test5/tb.gtkw[Renamed from verilog/dv/caravel/hs32_soc/core1test5/tb.gtkw - diff]
verilog/dv/caravel/hs32_soc/test5/test5.c[Renamed from verilog/dv/caravel/hs32_soc/core1test5/test5.c - diff]
verilog/dv/caravel/hs32_soc/test5/test5_tb.v[Renamed from verilog/dv/caravel/hs32_soc/core1test5/test5_tb.v - diff]
verilog/dv/caravel/hs32_soc/test6/Makefile[Renamed from verilog/dv/caravel/hs32_soc/core1test6/Makefile - diff]
verilog/dv/caravel/hs32_soc/test6/README.md[Renamed from verilog/dv/caravel/hs32_soc/core1test6/README.md - diff]
verilog/dv/caravel/hs32_soc/test6/tb.gtkw[Renamed from verilog/dv/caravel/hs32_soc/core1test6/tb.gtkw - diff]
verilog/dv/caravel/hs32_soc/test6/test6.c[Renamed from verilog/dv/caravel/hs32_soc/core1test6/test6.c - diff]
verilog/dv/caravel/hs32_soc/test6/test6_tb.v[Renamed from verilog/dv/caravel/hs32_soc/core1test6/test6_tb.v - diff]
verilog/dv/caravel/hs32_soc/test7/Makefile[Renamed from verilog/dv/caravel/hs32_soc/core1test7/Makefile - diff]
verilog/dv/caravel/hs32_soc/test7/README.md[Renamed from verilog/dv/caravel/hs32_soc/core1test7/README.md - diff]
verilog/dv/caravel/hs32_soc/test7/tb.gtkw[Renamed from verilog/dv/caravel/hs32_soc/core1test7/tb.gtkw - diff]
verilog/dv/caravel/hs32_soc/test7/test7.c[Renamed from verilog/dv/caravel/hs32_soc/core1test7/test7.c - diff]
verilog/dv/caravel/hs32_soc/test7/test7_tb.v[Renamed from verilog/dv/caravel/hs32_soc/core1test7/test7_tb.v - diff]
verilog/dv/caravel/hs32_soc/test8/Makefile[Renamed from verilog/dv/caravel/hs32_soc/core1test8/Makefile - diff]
verilog/dv/caravel/hs32_soc/test8/README.md[Renamed from verilog/dv/caravel/hs32_soc/core1test8/README.md - diff]
verilog/dv/caravel/hs32_soc/test8/tb.gtkw[Renamed from verilog/dv/caravel/hs32_soc/core1test8/tb.gtkw - diff]
verilog/dv/caravel/hs32_soc/test8/test6.c[Renamed from verilog/dv/caravel/hs32_soc/core1test8/test6.c - diff]
verilog/dv/caravel/hs32_soc/test8/test6_tb.v[Renamed from verilog/dv/caravel/hs32_soc/core1test8/test6_tb.v - diff]
verilog/dv/caravel/hs32_soc/testmem/Makefile[Renamed from verilog/dv/caravel/hs32_soc/core1mem/Makefile - diff]
verilog/dv/caravel/hs32_soc/testmem/README.md[Renamed from verilog/dv/caravel/hs32_soc/core1mem/README.md - diff]
verilog/dv/caravel/hs32_soc/testmem/mem.c[Renamed from verilog/dv/caravel/hs32_soc/core1mem/mem.c - diff]
verilog/dv/caravel/hs32_soc/testmem/mem_tb.v[Renamed from verilog/dv/caravel/hs32_soc/core1mem/mem_tb.v - diff]
verilog/dv/caravel/hs32_soc/testmem/tb.gtkw[Renamed from verilog/dv/caravel/hs32_soc/core1mem/tb.gtkw - diff]
verilog/dv/hs32_nocaravel/mmiotest/tb.gtkw[diff]

46 files changed

tree: fe3300793cb2b9abfd11a9c565adf8240baeba5d

README.md

HSC Latte HS32 Core

The HSC Latte HS32 Core is a 32-bits RISC CPU. The HS32 Core has 32-bits instructions and 16 32-bits registers.

Below is a list of HS32 Core Project Directories:

Repository	Description	License	Issues	Stars	Contributors
caravel-hs32core	Core Harness
hs32core-rtl	RTL Circuit Design
hs32core	Main Project Repository

HSC Latte HS32 Core

Overview

HS32 is a RISC-type CPU. (...)

Block Diagram Overview

CPU Overview

Execution Unit Block Diagram

Execution Unit

Project Structure

Path	Description
`verilog/rtl/hs32cpu`	CPU Core Submodule
`verilog/rtl/hs32_user_proj`	User project files and wrapper
`verilog/rtl/hs32cpu/docs`	Detailed core documentation
`verilog/dv/hs32_nocaravel`	No-caravel testbenches
`verilog/dv/caravel/hs32_soc`	Caravel-integrated testbenches

General Documentation

Instructions

Immediate value is 16-bits
Rd, Rn and Rm specify the way each register is wired to the ALU. In this case, Rd represents the read/write source/destination, Rm and Rn represents the 2 operands fed into the ALU; note that Rn will always have a barrel shifter in front of it.
Naming a register with Rd Rn Rm is always 4 bits
[xxx] = Dereference pointer, address is stored in xxx
sh(Rn) shifts contents of Rn left or right by an 5-bits amount

Encoding

These are the different encodings that instructions come in. All instructions are 32 bit. The first 8 bits is opcode. Rd, Rm, Rn are always in the same position in the instruciton if present indicates unused spacer value of X bits

Field Sizes:
- Rd : 4 bit register name
- Rm : 4 bit register name
- Rn : 4 bit register name
- Shift: 5 bit shift amount applied to Rn
- Imm16: 16 bit literal field

System Details

There are 16 (r0-r15) general-purpose registers plus 4 privileged registers. In supervisor mode, r12-15 is separate from user-mode r12-15. In all modes, r14 and r15 will be used as the link register and stack pointer respectively.

Legend:

IRQs -- Interrupt Requests
SP -- Stack Pointer
LR -- Link Register
MCR -- Machine Configuration Register
IVT -- Interrupt Vector Table

Operation

During a mode switch, the return address will be stored in the appropriate LR and the return stack pointer will be stored in the appropriate SP.

For instance, an interrupt call from User mode will prompt a switch to IRQ mode. The return address and stack pointer of the caller will be stored in IRQ LR (r14) and IRQ SP (r15) respectively.

CPU Planned Pinout

WIP

Devboard Block Diagram

Timing Waveforms

Various timing diagrams of the address and data buses

Read Cycle

Clock Cycles: 4 minimum

Timing Requirements:

The duration of the TW read clock (no data input) is determined by the tpd of whichever memory chip used.
TW can span multiple clock periods to allow for different memory timings. This will allow the CPU to be clocked at a higher speed than the memory chips.

In the implementation, OE# is the AND of 2 signals, one leading edge and one falling edge-driven signals.

Write Cycle