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foss-eda-tools/third_party/shuttle/sky130/mpw-001/slot-008/9de7415318bb55b7f35b8b73177299f7c36f2185^!/.
commit
9de7415318bb55b7f35b8b73177299f7c36f2185
[log]
author
Kevin <kevindai02@outlook.com>
Tue Dec 22 17:41:12 2020 -0500
committer
Kevin <kevindai02@outlook.com>
Tue Dec 22 17:41:12 2020 -0500
tree
fe3300793cb2b9abfd11a9c565adf8240baeba5d
parent
032cf31720f80e65f4442d33b9791aa9775b60a4 [diff]
Updated test structures

diff --git a/verilog/dv/caravel/hs32_soc/core1test1/Makefile b/verilog/dv/caravel/hs32_soc/test1/Makefile
similarity index 87%
rename from verilog/dv/caravel/hs32_soc/core1test1/Makefile
rename to verilog/dv/caravel/hs32_soc/test1/Makefile
index 37e9da3..7fa7302 100644
--- a/verilog/dv/caravel/hs32_soc/core1test1/Makefile
+++ b/verilog/dv/caravel/hs32_soc/test1/Makefile

@@ -1,6 +1,5 @@
-FIRMWARE_PATH = ../..
+FIRMWARE_PATH = ../../
 RTL_PATH = ../../../../rtl
-IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 VERILOG_PATH = ../../../../
 
@@ -21,16 +20,16 @@
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
 	iverilog -DSIM -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
 	-I $(RTL_PATH)/hs32cpu $< -o $@
 else
 	iverilog -DSIM -DFUNCTIONAL -DGL_SIM -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
 	-I $(RTL_PATH)/hs32cpu -I $(VERILOG_PATH) $< -o $@
 endif
 
 %.vcd: %.vvp
-	vvp $< -fst-speed
+	vvp $< -fst-speed $(OPT)
 
 %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
 	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<

diff --git a/verilog/dv/caravel/hs32_soc/core1test1/README.md b/verilog/dv/caravel/hs32_soc/test1/README.md
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test1/README.md
rename to verilog/dv/caravel/hs32_soc/test1/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test1/tb.gtkw b/verilog/dv/caravel/hs32_soc/test1/tb.gtkw
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test1/tb.gtkw
rename to verilog/dv/caravel/hs32_soc/test1/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test1/test1.c b/verilog/dv/caravel/hs32_soc/test1/test1.c
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test1/test1.c
rename to verilog/dv/caravel/hs32_soc/test1/test1.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test1/test1_tb.v b/verilog/dv/caravel/hs32_soc/test1/test1_tb.v
similarity index 92%
rename from verilog/dv/caravel/hs32_soc/core1test1/test1_tb.v
rename to verilog/dv/caravel/hs32_soc/test1/test1_tb.v
index a167e05..6e12574 100644
--- a/verilog/dv/caravel/hs32_soc/core1test1/test1_tb.v
+++ b/verilog/dv/caravel/hs32_soc/test1/test1_tb.v

@@ -12,6 +12,7 @@
 
 module tb();
 	parameter TEST_ID = 1;
+	parameter FILENAME = "test1.hex";
 
 	reg clock;
   	reg RSTB;
@@ -47,7 +48,11 @@
 `ifndef GL_SIM
 		if(failed) begin
 			$display("%c[1;31m",27);
-			$display("Test 1: Failed (timed out)!");
+			$display("Test %d: Failed (timed out)!", TEST_ID);
+			$display("%c[0m",27);
+		end else begin
+			$display("%c[1;32m",27);
+			$display("Test %d: Passed weak cases.", TEST_ID);
 			$display("%c[0m",27);
 		end
 `endif
@@ -86,7 +91,6 @@
 		wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[2] == 32'hCAFE);
 		failed = 0;
 	end
-
 	always @(*) begin
 		if(tb.uut.mprj.core1.core.EXEC.fault) begin
 			$display("%c[1;31m",27);
@@ -138,7 +142,7 @@
 	);
 
 	spiflash #(
-		.FILENAME("test1.hex")
+		.FILENAME(FILENAME)
 	) spiflash (
 		.csb(flash_csb),
 		.clk(flash_clk),

diff --git a/verilog/dv/caravel/hs32_soc/core1test2/Makefile b/verilog/dv/caravel/hs32_soc/test2/Makefile
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test2/Makefile
rename to verilog/dv/caravel/hs32_soc/test2/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test2/README.md b/verilog/dv/caravel/hs32_soc/test2/README.md
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test2/README.md
rename to verilog/dv/caravel/hs32_soc/test2/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test2/tb.gtkw b/verilog/dv/caravel/hs32_soc/test2/tb.gtkw
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test2/tb.gtkw
rename to verilog/dv/caravel/hs32_soc/test2/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test2/test2.c b/verilog/dv/caravel/hs32_soc/test2/test2.c
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test2/test2.c
rename to verilog/dv/caravel/hs32_soc/test2/test2.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test2/test2_tb.v b/verilog/dv/caravel/hs32_soc/test2/test2_tb.v
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test2/test2_tb.v
rename to verilog/dv/caravel/hs32_soc/test2/test2_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test3/Makefile b/verilog/dv/caravel/hs32_soc/test3/Makefile
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test3/Makefile
rename to verilog/dv/caravel/hs32_soc/test3/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test3/README.md b/verilog/dv/caravel/hs32_soc/test3/README.md
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test3/README.md
rename to verilog/dv/caravel/hs32_soc/test3/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test3/tb.gtkw b/verilog/dv/caravel/hs32_soc/test3/tb.gtkw
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test3/tb.gtkw
rename to verilog/dv/caravel/hs32_soc/test3/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test3/test3.c b/verilog/dv/caravel/hs32_soc/test3/test3.c
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test3/test3.c
rename to verilog/dv/caravel/hs32_soc/test3/test3.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test3/test3_tb.v b/verilog/dv/caravel/hs32_soc/test3/test3_tb.v
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test3/test3_tb.v
rename to verilog/dv/caravel/hs32_soc/test3/test3_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test4/Makefile b/verilog/dv/caravel/hs32_soc/test4/Makefile
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test4/Makefile
rename to verilog/dv/caravel/hs32_soc/test4/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test4/README.md b/verilog/dv/caravel/hs32_soc/test4/README.md
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test4/README.md
rename to verilog/dv/caravel/hs32_soc/test4/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test4/tb.gtkw b/verilog/dv/caravel/hs32_soc/test4/tb.gtkw
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test4/tb.gtkw
rename to verilog/dv/caravel/hs32_soc/test4/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test4/test4.c b/verilog/dv/caravel/hs32_soc/test4/test4.c
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test4/test4.c
rename to verilog/dv/caravel/hs32_soc/test4/test4.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test4/test4_tb.v b/verilog/dv/caravel/hs32_soc/test4/test4_tb.v
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test4/test4_tb.v
rename to verilog/dv/caravel/hs32_soc/test4/test4_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test5/Makefile b/verilog/dv/caravel/hs32_soc/test5/Makefile
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test5/Makefile
rename to verilog/dv/caravel/hs32_soc/test5/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test5/README.md b/verilog/dv/caravel/hs32_soc/test5/README.md
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test5/README.md
rename to verilog/dv/caravel/hs32_soc/test5/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test5/tb.gtkw b/verilog/dv/caravel/hs32_soc/test5/tb.gtkw
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test5/tb.gtkw
rename to verilog/dv/caravel/hs32_soc/test5/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test5/test5.c b/verilog/dv/caravel/hs32_soc/test5/test5.c
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test5/test5.c
rename to verilog/dv/caravel/hs32_soc/test5/test5.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test5/test5_tb.v b/verilog/dv/caravel/hs32_soc/test5/test5_tb.v
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test5/test5_tb.v
rename to verilog/dv/caravel/hs32_soc/test5/test5_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test6/Makefile b/verilog/dv/caravel/hs32_soc/test6/Makefile
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test6/Makefile
rename to verilog/dv/caravel/hs32_soc/test6/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test6/README.md b/verilog/dv/caravel/hs32_soc/test6/README.md
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test6/README.md
rename to verilog/dv/caravel/hs32_soc/test6/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test6/tb.gtkw b/verilog/dv/caravel/hs32_soc/test6/tb.gtkw
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test6/tb.gtkw
rename to verilog/dv/caravel/hs32_soc/test6/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test6/test6.c b/verilog/dv/caravel/hs32_soc/test6/test6.c
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test6/test6.c
rename to verilog/dv/caravel/hs32_soc/test6/test6.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test6/test6_tb.v b/verilog/dv/caravel/hs32_soc/test6/test6_tb.v
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test6/test6_tb.v
rename to verilog/dv/caravel/hs32_soc/test6/test6_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test7/Makefile b/verilog/dv/caravel/hs32_soc/test7/Makefile
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test7/Makefile
rename to verilog/dv/caravel/hs32_soc/test7/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test7/README.md b/verilog/dv/caravel/hs32_soc/test7/README.md
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test7/README.md
rename to verilog/dv/caravel/hs32_soc/test7/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test7/tb.gtkw b/verilog/dv/caravel/hs32_soc/test7/tb.gtkw
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test7/tb.gtkw
rename to verilog/dv/caravel/hs32_soc/test7/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test7/test7.c b/verilog/dv/caravel/hs32_soc/test7/test7.c
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test7/test7.c
rename to verilog/dv/caravel/hs32_soc/test7/test7.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test7/test7_tb.v b/verilog/dv/caravel/hs32_soc/test7/test7_tb.v
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test7/test7_tb.v
rename to verilog/dv/caravel/hs32_soc/test7/test7_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test8/Makefile b/verilog/dv/caravel/hs32_soc/test8/Makefile
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test8/Makefile
rename to verilog/dv/caravel/hs32_soc/test8/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test8/README.md b/verilog/dv/caravel/hs32_soc/test8/README.md
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test8/README.md
rename to verilog/dv/caravel/hs32_soc/test8/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test8/tb.gtkw b/verilog/dv/caravel/hs32_soc/test8/tb.gtkw
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test8/tb.gtkw
rename to verilog/dv/caravel/hs32_soc/test8/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test8/test6.c b/verilog/dv/caravel/hs32_soc/test8/test6.c
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test8/test6.c
rename to verilog/dv/caravel/hs32_soc/test8/test6.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test8/test6_tb.v b/verilog/dv/caravel/hs32_soc/test8/test6_tb.v
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test8/test6_tb.v
rename to verilog/dv/caravel/hs32_soc/test8/test6_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1mem/Makefile b/verilog/dv/caravel/hs32_soc/testmem/Makefile
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1mem/Makefile
rename to verilog/dv/caravel/hs32_soc/testmem/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1mem/README.md b/verilog/dv/caravel/hs32_soc/testmem/README.md
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1mem/README.md
rename to verilog/dv/caravel/hs32_soc/testmem/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1mem/mem.c b/verilog/dv/caravel/hs32_soc/testmem/mem.c
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1mem/mem.c
rename to verilog/dv/caravel/hs32_soc/testmem/mem.c

diff --git a/verilog/dv/caravel/hs32_soc/core1mem/mem_tb.v b/verilog/dv/caravel/hs32_soc/testmem/mem_tb.v
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1mem/mem_tb.v
rename to verilog/dv/caravel/hs32_soc/testmem/mem_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1mem/tb.gtkw b/verilog/dv/caravel/hs32_soc/testmem/tb.gtkw
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1mem/tb.gtkw
rename to verilog/dv/caravel/hs32_soc/testmem/tb.gtkw

diff --git a/verilog/dv/hs32_nocaravel/mmiotest/tb.gtkw b/verilog/dv/hs32_nocaravel/mmiotest/tb.gtkw
index ddfdf8c..98493dd 100644
--- a/verilog/dv/hs32_nocaravel/mmiotest/tb.gtkw
+++ b/verilog/dv/hs32_nocaravel/mmiotest/tb.gtkw

@@ -1,28 +1,69 @@
 [*]
 [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
-[*] Tue Dec 22 02:52:28 2020
+[*] Tue Dec 22 22:38:55 2020
 [*]
 [dumpfile] "/data/caravel-hs32core/verilog/dv/hs32_nocaravel/mmiotest/dump.fst"
-[dumpfile_mtime] "Tue Dec 22 02:49:24 2020"
-[dumpfile_size] 9941
+[dumpfile_mtime] "Tue Dec 22 22:34:50 2020"
+[dumpfile_size] 10579
 [savefile] "/data/caravel-hs32core/verilog/dv/hs32_nocaravel/mmiotest/tb.gtkw"
 [timestart] 0
-[size] 1000 600
-[pos] 318 63
-*-9.502302 370 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[size] 911 572
+[pos] 727 46
+*-7.502302 1660 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] tb.
 [treeopen] tb.mprj.
 [treeopen] tb.mprj.core1.
 [sst_width] 314
-[signals_width] 224
+[signals_width] 255
 [sst_expanded] 1
 [sst_vpaned_height] 151
 @28
 tb.mprj.core1.clk
 @22
 tb.mprj.core1.io_in[37:0]
-@28
+@c00028
 tb.mprj.core1.io_out[37:0]
+@28
+(0)tb.mprj.core1.io_out[37:0]
+(1)tb.mprj.core1.io_out[37:0]
+(2)tb.mprj.core1.io_out[37:0]
+(3)tb.mprj.core1.io_out[37:0]
+(4)tb.mprj.core1.io_out[37:0]
+(5)tb.mprj.core1.io_out[37:0]
+(6)tb.mprj.core1.io_out[37:0]
+(7)tb.mprj.core1.io_out[37:0]
+(8)tb.mprj.core1.io_out[37:0]
+(9)tb.mprj.core1.io_out[37:0]
+(10)tb.mprj.core1.io_out[37:0]
+(11)tb.mprj.core1.io_out[37:0]
+(12)tb.mprj.core1.io_out[37:0]
+(13)tb.mprj.core1.io_out[37:0]
+(14)tb.mprj.core1.io_out[37:0]
+(15)tb.mprj.core1.io_out[37:0]
+(16)tb.mprj.core1.io_out[37:0]
+(17)tb.mprj.core1.io_out[37:0]
+(18)tb.mprj.core1.io_out[37:0]
+(19)tb.mprj.core1.io_out[37:0]
+(20)tb.mprj.core1.io_out[37:0]
+(21)tb.mprj.core1.io_out[37:0]
+(22)tb.mprj.core1.io_out[37:0]
+(23)tb.mprj.core1.io_out[37:0]
+(24)tb.mprj.core1.io_out[37:0]
+(25)tb.mprj.core1.io_out[37:0]
+(26)tb.mprj.core1.io_out[37:0]
+(27)tb.mprj.core1.io_out[37:0]
+(28)tb.mprj.core1.io_out[37:0]
+(29)tb.mprj.core1.io_out[37:0]
+(30)tb.mprj.core1.io_out[37:0]
+(31)tb.mprj.core1.io_out[37:0]
+(32)tb.mprj.core1.io_out[37:0]
+(33)tb.mprj.core1.io_out[37:0]
+(34)tb.mprj.core1.io_out[37:0]
+(35)tb.mprj.core1.io_out[37:0]
+(36)tb.mprj.core1.io_out[37:0]
+(37)tb.mprj.core1.io_out[37:0]
+@1401200
+-group_end
 @200
 -
 @800200
@@ -86,15 +127,14 @@
 @28
 tb.mprj.core1.t0_io_oe
 tb.mprj.core1.t0_io_out
-tb.mprj.core1.t0_match_int
 tb.mprj.core1.t1_io_oe
 tb.mprj.core1.t1_io_out
-tb.mprj.core1.t1_match_int
 tb.mprj.core1.t2_io_oe
 tb.mprj.core1.t2_io_out
-tb.mprj.core1.t2_match_int
 @1401200
 -Timers
+@c00200
+-Timer0
 @28
 tb.mprj.core1.dev_timer0.clk
 @22
@@ -105,7 +145,20 @@
 @22
 tb.mprj.core1.dev_timer0.tconfig[6:0]
 tb.mprj.core1.dev_timer0.match[15:0]
-@29
+@28
 tb.mprj.core1.dev_timer0.addr[1:0]
+@1401200
+-Timer0
+@800200
+-WB Device
+@22
+tb.mprj.core1.wb.r_adr[31:0]
+@28
+tb.mprj.core1.wb.r_cfg[1:0]
+@22
+tb.mprj.core1.wb.r_dtr[31:0]
+tb.mprj.core1.wb.r_dtw[31:0]
+@1000200
+-WB Device
 [pattern_trace] 1
 [pattern_trace] 0