verilog/rtl/user_proj_example.v

// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//      http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0

`default_nettype none

`ifdef GL_SIM
    `include "gl/hs32_core1.v"
`else
    `include "cpu/hs32_cpu.v"
    
    `include "hs32_user_proj/hs32_core1.v"

    `include "hs32_user_proj/hs32_aic.v"
    `include "hs32_user_proj/hs32_bram_ctl.v"
    `include "hs32_user_proj/io_filter.v"
    `include "hs32_user_proj/dev_timer.v"
    `include "hs32_user_proj/dev_gpio.v"
    `include "hs32_user_proj/dev_wb.v"
    `include "hs32_user_proj/dev_intercon.v"
`endif