Merge conflict
diff --git a/macros/bm/sram_1rw1r_32_256_8_sky130.v b/macros/bm/sram_1rw1r_32_256_8_sky130.v new file mode 100644 index 0000000..09059a5 --- /dev/null +++ b/macros/bm/sram_1rw1r_32_256_8_sky130.v
@@ -0,0 +1,118 @@ +`default_nettype none +// OpenRAM SRAM model +// Words: 256 +// Word size: 32 +// Write size: 8 + +module sram_1rw1r_32_256_8_sky130( +`ifdef USE_POWER_PINS + vdd, + gnd, +`endif +// Port 0: RW + clk0,csb0,web0,wmask0,addr0,din0,dout0, +// Port 1: R + clk1,csb1,addr1,dout1 + ); + + parameter NUM_WMASKS = 4 ; + parameter DATA_WIDTH = 32 ; + parameter ADDR_WIDTH = 8 ; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + // FIXME: This delay is arbitrary. + parameter DELAY = 3 ; + +`ifdef USE_POWER_PINS + inout vdd; + inout gnd; +`endif + input clk0; // clock + input csb0; // active low chip select + input web0; // active low write control + input [NUM_WMASKS-1:0] wmask0; // write mask + input [ADDR_WIDTH-1:0] addr0; + input [DATA_WIDTH-1:0] din0; + output [DATA_WIDTH-1:0] dout0; + input clk1; // clock + input csb1; // active low chip select + input [ADDR_WIDTH-1:0] addr1; + output [DATA_WIDTH-1:0] dout1; + + reg csb0_reg; + reg web0_reg; + reg [NUM_WMASKS-1:0] wmask0_reg; + reg [ADDR_WIDTH-1:0] addr0_reg; + reg [DATA_WIDTH-1:0] din0_reg; + reg [DATA_WIDTH-1:0] dout0; + + // All inputs are registers + always @(posedge clk0) + begin + csb0_reg <= csb0; + web0_reg <= web0; + wmask0_reg <= wmask0; + addr0_reg <= addr0; + din0_reg <= din0; + dout0 <= 32'bx; +`ifdef DBG + if ( !csb0_reg && web0_reg ) + $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); + if ( !csb0_reg && !web0_reg ) + $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg); +`endif + end + + reg csb1_reg; + reg [ADDR_WIDTH-1:0] addr1_reg; + reg [DATA_WIDTH-1:0] dout1; + + // All inputs are registers + always @(posedge clk1) + begin + csb1_reg <= csb1; + addr1_reg <= addr1; +`ifdef DBG + if (!csb0 && !web0 && !csb1 && (addr0 == addr1)) + $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1); + dout1 = 32'bx; + if ( !csb1_reg ) + $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]); +`endif + end + +reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + + // Memory Write Block Port 0 + // Write Operation : When web0 = 0, csb0 = 0 + always @ (negedge clk0) + begin : MEM_WRITE0 + if ( !csb0_reg && !web0_reg ) begin + if (wmask0_reg[0]) + mem[addr0_reg][7:0] <= din0_reg[7:0]; + if (wmask0_reg[1]) + mem[addr0_reg][15:8] <= din0_reg[15:8]; + if (wmask0_reg[2]) + mem[addr0_reg][23:16] <= din0_reg[23:16]; + if (wmask0_reg[3]) + mem[addr0_reg][31:24] <= din0_reg[31:24]; + end + end + + // Memory Read Block Port 0 + // Read Operation : When web0 = 1, csb0 = 0 + always @ (negedge clk0) + begin : MEM_READ0 + if (!csb0_reg && web0_reg) + dout0 <= #(DELAY) mem[addr0_reg]; + end + + // Memory Read Block Port 1 + // Read Operation : When web1 = 1, csb1 = 0 + always @ (negedge clk1) + begin : MEM_READ1 + if (!csb1_reg) + dout1 <= #(DELAY) mem[addr1_reg]; + end + +endmodule +`default_nettype wire
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile index 3ab6272..2c6407d 100644 --- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile +++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
@@ -3,9 +3,9 @@ IP_PATH = ../../../../ip BEHAVIOURAL_MODELS = ../../ -GCC_PATH?=/ef/apps/bin +GCC_PATH?=/opt/riscv32i/bin GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A +PDK_PATH?=$(PDK_ROOT)/sky130A .SUFFIXES: @@ -16,7 +16,7 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ + iverilog -DSIM -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ -o $@ $<
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.hex b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.hex new file mode 100644 index 0000000..931dc5f --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.hex
@@ -0,0 +1,32 @@ +@00000000 +93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00 +13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00 +13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00 +13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00 +13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 +13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 +13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 +13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 85 17 +93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1 +11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00 +63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 71 28 +01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00 +A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00 +23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3 +F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F +00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01 +93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00 +93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00 +23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC +FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08 +A3 81 62 00 82 80 01 00 00 00 41 11 22 C6 00 08 +B7 07 00 26 93 87 07 02 09 67 13 07 87 80 98 C3 +B7 07 00 26 93 87 47 02 09 67 13 07 87 80 98 C3 +B7 07 00 26 93 87 87 02 09 67 13 07 87 80 98 C3 +B7 07 00 26 93 87 C7 02 09 67 13 07 87 80 98 C3 +B7 07 00 26 93 87 07 03 09 67 13 07 87 80 98 C3 +B7 07 00 26 93 87 47 03 09 67 13 07 87 80 98 C3 +B7 07 00 26 93 87 87 03 09 67 13 07 87 80 98 C3 +B7 07 00 26 93 87 C7 03 09 67 13 07 87 80 98 C3 +B7 07 00 26 05 47 98 C3 01 00 B7 07 00 26 98 43 +85 47 E3 0C F7 FE 01 00 32 44 41 01 82 80 00 00
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.vcd b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.vcd new file mode 100644 index 0000000..b0472cd --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.vcd Binary files differ
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1.hex b/verilog/dv/caravel/user_proj_example/la_test1/la_test1.hex new file mode 100644 index 0000000..5dfca2f --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1.hex
@@ -0,0 +1,75 @@ +@00000000 +93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00 +13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00 +13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00 +13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00 +13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 +13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 +13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 +13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 C5 41 +93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1 +11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00 +63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 11 22 +01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00 +A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00 +23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3 +F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F +00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01 +93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00 +93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00 +23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC +FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08 +A3 81 62 00 82 80 01 00 00 00 01 11 06 CE 22 CC +00 10 AA 87 A3 07 F4 FE 03 47 F4 FE A9 47 63 14 +F7 00 35 45 DD 37 B7 07 00 20 91 07 03 47 F4 FE +98 C3 01 00 F2 40 62 44 05 61 82 80 01 11 06 CE +22 CC 00 10 23 26 A4 FE 19 A8 83 27 C4 FE 13 87 +17 00 23 26 E4 FE 83 C7 07 00 3E 85 7D 37 83 27 +C4 FE 83 C7 07 00 F5 F3 01 00 F2 40 62 44 05 61 +82 80 41 11 06 C6 22 C4 00 08 B7 07 00 26 93 87 +C7 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +87 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +47 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +07 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +C7 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +87 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +47 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +07 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +C7 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +87 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +47 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +07 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +C7 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +87 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +47 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +07 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +C7 05 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +87 05 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +47 05 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +07 05 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +C7 04 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +87 04 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +47 04 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +07 04 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +C7 03 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +47 03 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +07 03 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +C7 02 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +87 02 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +47 02 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +07 02 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +87 03 09 67 13 07 97 80 98 C3 B7 07 00 20 13 07 +10 27 98 C3 B7 07 00 20 A1 07 05 47 98 C3 B7 07 +00 26 05 47 98 C3 01 00 B7 07 00 26 98 43 85 47 +E3 0C F7 FE B7 07 00 25 C1 07 7D 57 98 C3 B7 07 +00 25 D1 07 23 A0 07 00 B7 07 00 25 E1 07 7D 57 +98 C3 B7 07 00 25 F1 07 7D 57 98 C3 B7 07 00 26 +A1 07 37 07 40 AB 98 C3 B7 07 00 25 91 07 23 A0 +07 00 B7 07 00 25 D1 07 7D 57 98 C3 B7 07 00 25 +98 43 93 07 40 1F E3 FB E7 FE B7 07 00 26 A1 07 +37 07 41 AB 98 C3 01 00 B7 07 00 10 13 85 47 47 +35 33 B7 07 00 10 13 85 87 47 0D 33 B7 07 00 26 +A1 07 37 07 51 AB 98 C3 01 00 B2 40 22 44 41 01 +82 80 00 00 0A 00 00 00 4D 6F 6E 69 74 6F 72 3A +20 54 65 73 74 20 32 20 50 61 73 73 65 64 0A 0A +00 00 00 00
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2.hex b/verilog/dv/caravel/user_proj_example/la_test2/la_test2.hex new file mode 100644 index 0000000..34075a5 --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/la_test2/la_test2.hex
@@ -0,0 +1,71 @@ +@00000000 +93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00 +13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00 +13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00 +13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00 +13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 +13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 +13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 +13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 85 3E +93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1 +11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 80 00 +63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 11 22 +01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00 +A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00 +23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3 +F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F +00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01 +93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00 +93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00 +23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC +FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08 +A3 81 62 00 82 80 01 00 00 00 01 11 06 CE 22 CC +00 10 AA 87 A3 07 F4 FE 03 47 F4 FE A9 47 63 14 +F7 00 35 45 DD 37 B7 07 00 20 91 07 03 47 F4 FE +98 C3 01 00 F2 40 62 44 05 61 82 80 01 11 06 CE +22 CC 00 10 23 26 A4 FE 19 A8 83 27 C4 FE 13 87 +17 00 23 26 E4 FE 83 C7 07 00 3E 85 7D 37 83 27 +C4 FE 83 C7 07 00 F5 F3 01 00 F2 40 62 44 05 61 +82 80 41 11 22 C6 00 08 B7 07 00 26 93 87 C7 09 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 87 09 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 47 09 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 07 09 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 C7 08 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 87 08 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 47 08 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 07 08 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 C7 07 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 87 07 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 47 07 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 07 07 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 C7 06 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 87 06 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 47 06 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 07 06 +09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 C7 05 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 87 05 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 47 05 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 07 05 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 C7 04 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 87 04 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 47 04 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 07 04 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 C7 03 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 47 03 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 07 03 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 C7 02 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 87 02 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 47 02 +09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 07 02 +09 67 13 07 87 80 98 C3 B7 07 00 26 05 47 98 C3 +01 00 B7 07 00 26 98 43 85 47 E3 0C F7 FE B7 07 +00 25 C1 07 7D 57 98 C3 B7 07 00 25 D1 07 7D 57 +98 C3 B7 07 00 25 E1 07 7D 57 98 C3 B7 07 00 25 +F1 07 7D 57 98 C3 B7 07 00 26 A1 07 37 07 60 AB +98 C3 B7 07 00 25 E1 07 71 57 98 C3 B7 07 00 25 +A1 07 0D 47 98 C3 23 22 00 00 35 A0 83 27 00 00 +93 B7 17 00 93 F7 F7 0F 3E 87 23 20 E0 00 03 27 +00 00 B7 07 00 25 A1 07 98 C3 83 27 40 00 13 87 +17 00 23 22 E0 00 03 27 40 00 A9 47 E3 D8 E7 FC +B7 07 00 25 98 43 95 47 63 18 F7 00 B7 07 00 26 +A1 07 37 07 61 AB 98 C3 01 00 32 44 41 01 82 80
diff --git a/verilog/dv/caravel/user_proj_example/verify.log b/verilog/dv/caravel/user_proj_example/verify.log new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/verify.log
diff --git a/verilog/rtl/hs32_user_proj/hs32_wrapper.v b/verilog/rtl/hs32_user_proj/hs32_wrapper.v index 7822e73..b513718 100644 --- a/verilog/rtl/hs32_user_proj/hs32_wrapper.v +++ b/verilog/rtl/hs32_user_proj/hs32_wrapper.v
@@ -1,7 +1,7 @@ `ifdef verilator `include "defines.v" `include "hs32_user_proj/hs32_core1.v" - `include "sram_1rw1r_32_256_8_sky130.v" + `include "../../macros/bm/sram_1rw1r_32_256_8_sky130.v" `endif `default_nettype none