Worked on verification

.gitignore

diff --git a/.gitignore b/.gitignore
index 62b8813..144d6b6 100644
--- a/.gitignore
+++ b/.gitignore
@@ -6,3 +6,4 @@
 *.elf
 *.bin
 *.vvp
+*.idx

macros/bm/sram_1rw1r_32_256_8_sky130.v

diff --git a/macros/bm/sram_1rw1r_32_256_8_sky130.v b/macros/bm/sram_1rw1r_32_256_8_sky130.v
index fc0e454..d87acb8 100644
--- a/macros/bm/sram_1rw1r_32_256_8_sky130.v
+++ b/macros/bm/sram_1rw1r_32_256_8_sky130.v
@@ -54,12 +54,12 @@
     addr0_reg <= addr0;
     din0_reg <= din0;
     dout0 <= 32'bx;
-//`ifdef DBG
+`ifdef DBG1
     if ( !csb0_reg && web0_reg ) 
-      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+      $display($time," Reading %m addr0=%X dout0=%X",addr0_reg,mem[addr0_reg]);
     if ( !csb0_reg && !web0_reg )
-      $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
-//`endif 
+      $display($time," Writing %m addr0=%X din0=%X wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+`endif
    end
 
   reg  csb1_reg;

verilog/dv/caravel/hs32_soc/core1test1/core1.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test1/core1.c b/verilog/dv/caravel/hs32_soc/core1test1/core1.c
index 2a6b6a2..9a43a72 100644
--- a/verilog/dv/caravel/hs32_soc/core1test1/core1.c
+++ b/verilog/dv/caravel/hs32_soc/core1test1/core1.c
@@ -1,11 +1,5 @@
 #include "../../defs.h"
 
-/*
-	IO Test:
-		- Configures MPRJ lower 8-IO pins as outputs
-		- Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
-*/
-
 void main()
 {
 	// Reset
@@ -13,6 +7,8 @@
 	reg_la1_ena = 0xFFFFFFFF;    // [63:32]
 	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
 	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
+	
+	// Reset and control bus
 	reg_la0_data = 0b01;
 	reg_la0_data = 0b00;
 
@@ -24,6 +20,10 @@
 	((volatile uint32_t*) 0x30000000)[4] = 0x22010000;
 	((volatile uint32_t*) 0x30000000)[5] = 0x21200000;
 
+	// Release control
+	reg_la0_data = 0b11;
+	reg_la0_data = 0b10;
+
 	// Configure lower 8-IOs as user output
 	// Observe counter value in the testbench
 	reg_mprj_io_0 =  GPIO_MODE_USER_STD_OUTPUT;

verilog/dv/caravel/hs32_soc/core1test1/core1_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test1/core1_tb.v b/verilog/dv/caravel/hs32_soc/core1test1/core1_tb.v
index ac36b00..bd68e0d 100644
--- a/verilog/dv/caravel/hs32_soc/core1test1/core1_tb.v
+++ b/verilog/dv/caravel/hs32_soc/core1test1/core1_tb.v
@@ -1,3 +1,5 @@
+`define DBG1
+
 `default_nettype none
 
 `timescale 1 ns / 1 ns

verilog/rtl/hs32_user_proj/hs32_core1.v

diff --git a/verilog/rtl/hs32_user_proj/hs32_core1.v b/verilog/rtl/hs32_user_proj/hs32_core1.v
index 0883c3e..e940b14 100644
--- a/verilog/rtl/hs32_user_proj/hs32_core1.v
+++ b/verilog/rtl/hs32_user_proj/hs32_core1.v
@@ -116,8 +116,7 @@
     assign cpu_ack = bus_hold ? 0: ack;
 
     reg bsy;
-    assign ram_ce = ~bsy;
-`ifdef SIM
+    assign ram_ce = ~(stb | bsy);
     always @(posedge clk) if(rst)
         bsy <= 0;
     else begin
@@ -125,13 +124,15 @@
             bsy <= 1;
         end else if(ack && bsy) begin
             bsy <= 0;
-        end
-        /*if(!stb && !rw)
-            $display($time, " Reading %X %X", addr, dread);
-        if(!stb && rw)
-            $display($time, " Writing %X %X", addr, dwrite);*/
-    end
+`ifndef DBG1
+            if(rw) begin
+                $display($time, " Writing %X %X", addr, dwrite);
+            end else begin
+                $display($time, " Reading %X %X", addr, dread);
+            end
 `endif
+        end
+    end
 
     //===============================//
     // MMIO and Interrupts

verilog/rtl/hs32cpu

diff --git a/verilog/rtl/hs32cpu b/verilog/rtl/hs32cpu
index 512eeba..0d18a8d 160000
--- a/verilog/rtl/hs32cpu
+++ b/verilog/rtl/hs32cpu
@@ -1 +1 @@
-Subproject commit 512eeba101ecedd60a5466e57a7ef15f5229cd83
+Subproject commit 0d18a8d624373d4b7929d92b7dfcbec2b6c3acd1