Add README
diff --git a/LICENSE b/LICENSE index d645695..75b5248 100644 --- a/LICENSE +++ b/LICENSE
@@ -1,202 +1,202 @@ - - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. Definitions. - - "License" shall mean the terms and conditions for use, reproduction, - and distribution as defined by Sections 1 through 9 of this document. - - "Licensor" shall mean the copyright owner or entity authorized by - the copyright owner that is granting the License. - - "Legal Entity" shall mean the union of the acting entity and all - other entities that control, are controlled by, or are under common - control with that entity. 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However, in accepting such obligations, You may act only - on Your own behalf and on Your sole responsibility, not on behalf - of any other Contributor, and only if You agree to indemnify, - defend, and hold each Contributor harmless for any liability - incurred by, or claims asserted against, such Contributor by reason - of your accepting any such warranty or additional liability. - - END OF TERMS AND CONDITIONS - - APPENDIX: How to apply the Apache License to your work. - - To apply the Apache License to your work, attach the following - boilerplate notice, with the fields enclosed by brackets "[]" - replaced with your own identifying information. (Don't include - the brackets!) The text should be enclosed in the appropriate - comment syntax for the file format. We also recommend that a - file or class name and description of purpose be included on the - same "printed page" as the copyright notice for easier - identification within third-party archives. - - Copyright [yyyy] [name of copyright owner] - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. For the purposes of this definition, + "control" means (i) the power, direct or indirect, to cause the + direction or management of such entity, whether by contract or + otherwise, or (ii) ownership of fifty percent (50%) or more of the + outstanding shares, or (iii) beneficial ownership of such entity. + + "You" (or "Your") shall mean an individual or Legal Entity + exercising permissions granted by this License. + + "Source" form shall mean the preferred form for making modifications, + including but not limited to software source code, documentation + source, and configuration files. + + "Object" form shall mean any form resulting from mechanical + transformation or translation of a Source form, including but + not limited to compiled object code, generated documentation, + and conversions to other media types. + + "Work" shall mean the work of authorship, whether in Source or + Object form, made available under the License, as indicated by a + copyright notice that is included in or attached to the work + (an example is provided in the Appendix below). + + "Derivative Works" shall mean any work, whether in Source or Object + form, that is based on (or derived from) the Work and for which the + editorial revisions, annotations, elaborations, or other modifications + represent, as a whole, an original work of authorship. For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. For the purposes of this definition, "submitted" + means any form of electronic, verbal, or written communication sent + to the Licensor or its representatives, including but not limited to + communication on electronic mailing lists, source code control systems, + and issue tracking systems that are managed by, or on behalf of, the + Licensor for the purpose of discussing and improving the Work, but + excluding communication that is conspicuously marked or otherwise + designated in writing by the copyright owner as "Not a Contribution." + + "Contributor" shall mean Licensor and any individual or Legal Entity + on behalf of whom a Contribution has been received by Licensor and + subsequently incorporated within the Work. + + 2. Grant of Copyright License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare Derivative Works of, + publicly display, publicly perform, sublicense, and distribute the + Work and such Derivative Works in Source or Object form. + + 3. Grant of Patent License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + (except as stated in this section) patent license to make, have made, + use, offer to sell, sell, import, and otherwise transfer the Work, + where such license applies only to those patent claims licensable + by such Contributor that are necessarily infringed by their + Contribution(s) alone or by combination of their Contribution(s) + with the Work to which such Contribution(s) was submitted. If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. The contents + of the NOTICE file are for informational purposes only and + do not modify the License. You may add Your own attribution + notices within Derivative Works that You distribute, alongside + or as an addendum to the NOTICE text from the Work, provided + that such additional attribution notices cannot be construed + as modifying the License. + + You may add Your own copyright statement to Your modifications and + may provide additional or different license terms and conditions + for use, reproduction, or distribution of Your modifications, or + for any such Derivative Works as a whole, provided Your use, + reproduction, and distribution of the Work otherwise complies with + the conditions stated in this License. + + 5. Submission of Contributions. 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Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License.
diff --git a/README.md b/README.md index 8b13789..d468cc2 100644 --- a/README.md +++ b/README.md
@@ -1 +1,312 @@ +# HSC Latte HS32 Core +The HSC Latte HS32 Core is a 32-bits RISC CPU. The HS32 Core has 32-bits instructions and 16 32-bits registers. + +Below is a list of HS32 Core Project Directories: + +| Repository | Description | License | Issues | Stars | Contributors | +| ----------------------------------------------------------------- | ----------------------- | ---------------------------------------------------------------------------- | -------------------------------------------------------------------------- | ------------------------------------------------------------------------ | -------------------------------------------------------------------------------------- | +| [caravel-hs32core](https://github.com/hsc-latte/caravel-hs32core) | Core Harness |  |  |  |  | +| [hs32core-rtl](https://github.com/hsc-latte/hs32core-rtl) | RTL Circuit Design |  |  |  |  | +| [hs32core](https://github.com/hsc-latte/hs32core) | Main Project Repository |  |  |  |  | + +## Content +1. [Intro](#intro) +2. [Docs](#docs) +3. [Install](#install) +4. [Usage](#usage) +5. [Contributing](#contributing) +6. [Security](#security) +7. [License](#license) + +## Intro + +### Instructions + +- Immediate value is 16-bits +- Rd, Rn and Rm specify the way each register is wired to the ALU. In this case, + Rd represents the read/write source/destination, Rm and Rn represents the 2 operands fed into the ALU; note that Rn will always have a barrel + shifter in front of it. +- Naming a register with Rd Rn Rm is always 4 bits +- [xxx] = Dereference pointer, address is stored in xxx +- sh(Rn) shifts contents of Rn left or right by an 5-bits amount + +#### Encoding + +These are the different encodings that instructions come in. +All instructions are 32 bit. +The first 8 bits is opcode. +Rd, Rm, Rn are always in the same position in the instruciton if present +<X> indicates unused spacer value of X bits + +- Field Sizes: + - Rd : 4 bit register name + - Rm : 4 bit register name + - Rn : 4 bit register name + - Shift: 5 bit shift amount applied to Rn + - Imm16: 16 bit literal field + +<div class="ritz grid-container" dir="ltr"><table class="waffle" cellspacing="0" cellpadding="0"><thead><tr><th class="row-header freezebar-origin-ltr"></th> + <th id="1092009867C0" style="width:121px" class="column-headers-background">A</th> + <th id="1092009867C1" style="width:100px" class="column-headers-background">B</th> + <th id="1092009867C2" style="width:100px" class="column-headers-background">C</th> + <th id="1092009867C3" style="width:100px" class="column-headers-background">D</th> + <th id="1092009867C4" style="width:100px" class="column-headers-background">E</th> + <th id="1092009867C5" style="width:100px" class="column-headers-background">F</th> + <th id="1092009867C6" style="width:100px" class="column-headers-background">G</th> + <th id="1092009867C7" style="width:100px" class="column-headers-background">H</th> + <th id="1092009867C8" style="width:100px" class="column-headers-background">I</th></tr></thead><tbody> + +<tr style='height:20px;'> + <th id="1092009867R0" style="height: 20px;" class="row-headers-background"> + <div class="row-header-wrapper" style="line-height: 20px;">1</div> + </th> + <td class="s0" dir="ltr">Name</td> + <td class="s0" dir="ltr">[0:3] </td> + <td class="s0" dir="ltr">[4:7] </td> + <td class="s0" dir="ltr">[8:11] </td> + <td class="s0" dir="ltr">[12:15]</td> + <td class="s0" dir="ltr">[16:19]</td> + <td class="s0" dir="ltr">[20:23]</td> + <td class="s0" dir="ltr">[24:27]</td> + <td class="s0" dir="ltr">[28:31]</td> +</tr> + +<tr style='height:20px;'> + <th id="1092009867R1" style="height: 20px;" class="row-headers-background"> + <div class="row-header-wrapper" style="line-height: 20px;">2</div> + </th> + <td class="s1" dir="ltr">I-Type<br/>(Immediate)</td> + <td class="s0" dir="ltr" colspan="2">Opcode</td> + <td class="s0" dir="ltr">Rd</td> + <td class="s0" dir="ltr">Rm</td> + <td class="s0" dir="ltr" colspan="4">Imm16</td> +</tr> + +<tr style='height:20px;'> + <th id="1092009867R3" style="height: 20px;" class="row-headers-background"> + <div class="row-header-wrapper" style="line-height: 20px;">5</div> + </th> + <td class="s0" dir="ltr">R-Type<br/>(Register)</td> + <td class="s0" dir="ltr" colspan="2">Opcode</td> + <td class="s0" dir="ltr" colspan="1">Rd</td> + <td class="s0" dir="ltr" colspan="1">Rm</td> + <td class="s0" dir="ltr" colspan="1">Rn</td> + <td class="s0" dir="ltr" colspan="1">Shift</td> + <td class="s0" dir="ltr" colspan="1">Shift | Shift Direction | Register Bank</td> + <td class="s0" dir="ltr" colspan="1">Register Bank | XXX</td> +</tr> + +<!--<tr style='height:20px;'> + <th id="1092009867R3" style="height: 20px;" class="row-headers-background"> + <div class="row-header-wrapper" style="line-height: 20px;">6</div> + </th> + <td class="s0" dir="ltr">Jump Type (J-Type)</td> + <td class="s0" dir="ltr" colspan="2">Opcode</td> + <td class="s0" dir="ltr" colspan="1">Rd</td> + <td class="s0" dir="ltr" colspan="1">Unused</td> + <td class="s0" dir="ltr" colspan="4">16-bit Address or first half of 32-bit Address</td> +</tr>--> +</tbody></table></div> + +#### System Details + +There are 16 (r0-r15) general-purpose registers plus 4 privileged registers. +In supervisor mode, r12-15 is separate from user-mode r12-15. In all modes, r14 and r15 will be used as the link register and stack pointer respectively. + +Legend: + +- **IRQs** -- Interrupt Requests +- **SP** -- Stack Pointer +- **LR** -- Link Register +- **MCR** -- Machine Configuration Register +- **IVT** -- Interrupt Vector Table + +<table border=0 cellpadding=0 cellspacing=0 width=543> + <tr height=19> + <td rowspan=2 height=38 width=64>Register</td> + <td colspan=3 width=287>Alias/Description</td> + </tr> + <tr height=19> + <td height=19>User</td> + <td>IRQ</td> + <td>Supervisor</td> + </tr> + <tr height=19> + <td height=19>r0-r11</td> + <td colspan=3><center>Shared general purpose registers</center></td> + </tr> + <tr height=19> + <td height=19>r12</td> + <td>General</td> + <td colspan=2><center>Interrupt Vector Table</center></td> + </tr> + <tr height=19> + <td height=19>r13</td> + <td>General</td> + <td colspan=2><center>Machine Configuration Register</center></td> + </tr> + <tr height=19> + <td height=19>r14</td> + <td>User LR</td> + <td>IRQ LR</td> + <td>Super LR</td> + </tr> + <tr height=19> + <td height=19>r15</td> + <td>User SP</td> + <td>IRQ SP</td> + <td>Super SP</td> + </tr> +</table> + +##### Operation + +During a mode switch, the return address will be stored in the appropriate LR and the return stack pointer will be stored in the appropriate SP. + +For instance, an interrupt call from User mode will prompt a switch to IRQ mode. The return address and stack pointer of the caller will be stored in IRQ LR (r14) and IRQ SP (r15) respectively. + +### CPU + +#### Planned Pinout + +| Pin # | Name | Description | +|-|-|-| +| 0-15 | IO0-15 | **Address/Data Parallel Bus:** These lines contain the time-multiplexed address (T<sub>1</sub>, T<sub>2</sub>)<br>and data (T<sub>W</sub>, T<sub>4</sub>) buses. During the T<sub>1</sub> cycle, bits A<sub>0</sub>-A<sub>7</sub> of the address bus is outputted.<br>Bit A<sub>0</sub> is the BLE# signal. It is LOW during T<sub>1</sub> if only the low 8-bits is to be transferred<br>during memory or I/O operations. | +| 16 | ALE0 | **Address Latch Enable (LOW):** HIGH during T<sub>1</sub> to signal for the latching of the low 8-bits<br>of the address signal. It is LOW otherwise. | +| 17 | ALE1 | **Address Latch Enable (HIGH):** HIGH during T<sub>2</sub> to signal for the latching of the high 8-bits<br>of the address signal. It is LOW otherwise. | +| 18 | WE# | **Write Enable:** Write strobe is LOW during T<sub>W</sub> to indicate that the processor is performing<br>an I/O or memory write operation. | +| 19 | OE# | **Output Enable:** When LOW, indicates that the processor IO lines are ready<br>to accept/output data. It is held HIGH during T<sub>1</sub> and T<sub>2</sub>. | +| 20 | BHE# | **Bus High Enable:** When LOW, signals for the high 8-bits to be transferred<br>during memory or I/O operations. | +| 22 | PIO | **IO Mode:** When HIGH, indicates that the current operation is an I/O, not memory, operation.<br>This results in the omittance of cycle T<sub>2</sub>. | +| 23, 24 | RX, TX | 9600 Baud UART Interface | +| 25-... | GPIO0-... | General Purpose Input/Output | + +#### Overview + + + +#### Devboard Block Diagram + + +#### Timing Waveforms + +Various timing diagrams of the address and data buses + +##### Read Cycle + +Clock Cycles: 4 minimum + +Timing Requirements: +- The duration of the T<sub>W</sub> read clock (no data input) is determined by the `tpd` of whichever memory chip used. +- T<sub>W</sub> can span multiple clock periods to allow for different memory timings. This will allow the CPU to be clocked at a higher speed than the memory chips. + +In the implementation, OE# is the AND of 2 signals, one leading edge and one falling edge-driven signals. + +<!-- WAVEDROM JSON FILE +{ signal: [ + { name: "CLK", wave: "hlhlhlhlhlh", node: "..1.2.3.4.5" }, + { name: "ALE0", wave: "xh.l......x" }, + { name: "ALE1", wave: "xl.h.l....." }, + { name: "WE#", wave: "h.........." }, + { name: "OE#", wave: "h.....l..h." }, + { name: "BHE#", wave: "x.h.......x" }, + { name: "IO[15:0]", wave: "x.9.9.x.5.x", data:[ "A[15:0]", "A[31:16]", "D[15:0]" ] },], + head: { text: "Figure 1. Read Cycle Timing Waveform" }, + edge: [ '1<->2 T1', '2<->3 T2', '3<->4 TW', '4<->5 T3' ] +} --> + + + +##### Write Cycle + +Clock Cycles: 4 minimum + +Timing Requirements: +- See the read cycle specifications + +<!-- WAVEDROM JSON FILE +{ signal: [ + { name: "CLK", wave: "hlhlhlhlhlh", node: "..1.2.3.4.5" }, + { name: "ALE0", wave: "xh.l......x" }, + { name: "ALE1", wave: "xl.h.l....." }, + { name: "WE#", wave: "h.....l.h.." }, + { name: "OE#", wave: "h.....l..h." }, + { name: "BHE#", wave: "x.h.......x" }, + { name: "IO[15:0]", wave: "x.9.9.7.x..", data:[ "A[15:0]", "A[31:16]", "D[15:0]" ] },], + head: { text: "Figure 2. Write Cycle Timing Waveform" }, + edge: [ '1<->2 T1', '2<->3 T2', '3<->4 TW', '4<->5 T3' ] +} --> + + +#### Execution Unit + + + +## Docs + +### Directories + +**HS32 RTL** -- [`verilog/rtl/hs32cpu`](https://github.com/hsc-latte/hs32core-rtl) + +**Documentation** -- [`verilog/rtl/hs32cpu/docs`](https://github.com/hsc-latte/hs32core-rtl/tree/master/docs) + +**Testbenches** -- [`verilog/rtl/hs32cpu/bench`](https://github.com/hsc-latte/hs32core-rtl/tree/master/bench) + +**CPU Modules** -- [`verilog/rtl/hs32cpu/cpu`](https://github.com/hsc-latte/hs32core-rtl/tree/master/cpu) + +**Frontend Modules** -- [`verilog/rtl/hs32cpu/frontend`](https://github.com/hsc-latte/hs32core-rtl/tree/master/frontend) + +**SOC Modules** -- [`verilog/rtl/hs32cpu/soc`](https://github.com/hsc-latte/hs32core-rtl/tree/master/soc) + +**Third Party Modules** -- [`verilog/rtl/hs32cpu/third_party`](https://github.com/hsc-latte/hs32core-rtl/tree/master/third_party) + +**Programmer** -- [`verilog/rtl/hs32cpu/programmer`](https://github.com/hsc-latte/hs32core-rtl/tree/master/programmer) + +**Openlane** -- [`verilog/rtl/hs32cpu/openlane`](https://github.com/hsc-latte/hs32core-rtl/tree/master/openlane) + +**Skywater** -- [`verilog/rtl/hs32cpu/skywater`](https://github.com/hsc-latte/hs32core-rtl/tree/master/skywater) + +### Files + +**HS32 ISA** -- [`verilog/rtl/hs32cpu/docs/isa_formal.txt`](https://github.com/hsc-latte/hs32core-rtl/tree/master/docs/isa_formal.txt) + +**Top Level Module** -- [`verilog/rtl/hs32cpu/top.v`](https://github.com/hsc-latte/hs32core-rtl/tree/master/top.v) + +**HS32 Interrupts** -- [`verilog/rtl/hs32cpu/docs/interrupts.md`](https://github.com/hsc-latte/hs32core-rtl/tree/master/docs/interrupts.md) + +**HS32 MMIO** -- [`verilog/rtl/hs32cpu/docs/mmio.md`](https://github.com/hsc-latte/hs32core-rtl/tree/master/docs/mmio.md) + +## Install + +## Usage + +## Contributing + +Issues and pull requests are welcome! Please make sure to create them at the right repository :D + +## Security + +We take any security risks seriously, if you have found or suspected a vulnerability or anything that might compromise our security, we would very much appreciate it if you can report it to us. + +## License + +Apache 2.0 [LICENSE](https://github.com/hsc-latte/hs32core-rtl/tree/master/LICENSE) + +HS32 Core - A 32-bits RISC Processor + +``` + Copyright (c) 2020 The HSC Core Authors + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + https://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +```
diff --git a/info.yaml b/info.yaml index 2a0898d..bc38ba5 100644 --- a/info.yaml +++ b/info.yaml
@@ -1,17 +1,17 @@ ---- -project: - description: "Open Source Hardware Processor" - foundry: "SkyWater" - git_url: "https://github.com/hsc-latte/caravel-hs32core.git" - organization: "HomebrewSiliconClub" - organization_url: "https://github.com/hsc-latte" - owner: "HomebrewSiliconClub" - process: "SKY130" - project_name: "HS32Core" - tags: - - "Open MPW" - category: "CPU" - top_level_netlist: "verilog/rtl/caravel.v" - user_level_netlist: "verilog/rtl/hs32cpu/top.v" - version: "1.00" - cover_image: "doc/ciic_harness.png" +--- +project: + description: "Open Source Hardware Processor" + foundry: "SkyWater" + git_url: "https://github.com/hsc-latte/caravel-hs32core.git" + organization: "HomebrewSiliconClub" + organization_url: "https://github.com/hsc-latte" + owner: "HomebrewSiliconClub" + process: "SKY130" + project_name: "HS32Core" + tags: + - "Open MPW" + category: "CPU" + top_level_netlist: "verilog/rtl/caravel.v" + user_level_netlist: "verilog/rtl/hs32cpu/top.v" + version: "1.00" + cover_image: "doc/ciic_harness.png"
diff --git a/verilog/rtl/hs32_user_proj/hs32_ram.v b/verilog/rtl/hs32_user_proj/hs32_ram.v index c35d0b2..40d444c 100644 --- a/verilog/rtl/hs32_user_proj/hs32_ram.v +++ b/verilog/rtl/hs32_user_proj/hs32_ram.v
@@ -1,95 +1,95 @@ -`ifdef verilator - `include "defines.v" -`endif - -`default_nettype none - -module storage ( - input wire clk, - input wire[addr_width-1:0] addr, - output reg [31:0] dread, - input wire[31:0] dwrite, - input wire rw, - input wire valid, - output reg ready -); - parameter addr_width = 8; - - // 4 addresses for each bram - // Selects between current dword and next dword - wire [addr_width-3:0] a0, a1, a2, a3; - assign a0 = (addr[1:0] == 2'b00) ? - addr[addr_width-1:2] : addr[addr_width-1:2] + 1; - assign a1 = (addr[1:0] == 2'b00) || (addr[1:0] == 2'b01) ? - addr[addr_width-1:2] : addr[addr_width-1:2] + 1; - assign a2 = (addr[1:0] == 2'b11) ? - addr[addr_width-1:2] + 1 : addr[addr_width-1:2]; - assign a3 = addr[addr_width-1:2]; - // - // The read buffer shifted over. - // Regarding the ending 2 bits of the address: - // x = read, . = ignore - // a' a'+1 -> where a' = addr[addr_width-1:2] - // 00 [xxxx][....] - // 01 [.xxx][x...] - // 10 [..xx][xx..] - // 11 [...x][xxx.] - // 0123 0123 -> bram# the byte came from - // dbuf will always be in the form of [0123] - // So, an address ending in 11 should be [3012] - // - wire[31:0] dout; - wire[31:0] dbuf, wbuf; - assign dout = - (addr[1:0] == 2'b00) ? { dbuf[31:0] } : - (addr[1:0] == 2'b01) ? { dbuf[23:0], dbuf[31:24] } : - (addr[1:0] == 2'b10) ? { dbuf[15:0], dbuf[31:16] } : - { dbuf[ 7:0], dbuf[31:8] } ; - assign wbuf = - (addr[1:0] == 2'b00) ? { dwrite[31:0] } : - (addr[1:0] == 2'b01) ? { dwrite[ 7:0], dwrite[31:8 ] } : - (addr[1:0] == 2'b10) ? { dwrite[15:0], dwrite[31:16] } : - { dwrite[23:0], dwrite[31:24] } ; - - // Write enable signal - wire we; assign we = valid & rw; - - // FSM (needed?) - reg[1:0] state = 0; - always @(posedge clk) case(state) - 0: begin - if(valid) begin - state <= 1; - end - ready <= 1; - dread <= dout; - end - 1: begin - state <= 0; - ready <= 0; - end - endcase - - sram_1rw1r_32_256_8_sky130 SRAM_0 ( - // MGMT R/W port - .clk0(clk), - .csb0(mgmt_ena[0]), - .web0(mgmt_wen[0]), - .wmask0(mgmt_wen_mask[3:0]), - .addr0(addr), - .din0(dwrite), - .dout0(dread) - ); - - sram_1rw1r_32_256_8_sky130 SRAM_1 ( - // MGMT R/W port - .clk0(mgmt_clk), - .csb0(mgmt_ena[1]), - .web0(mgmt_wen[1]), - .wmask0(mgmt_wen_mask[7:4]), - .addr0(mgmt_addr), - .din0(mgmt_wdata), - .dout0(mgmt_rdata[63:32]) - ); -endmodule -`default_nettype wire +`ifdef verilator + `include "defines.v" +`endif + +`default_nettype none + +module storage ( + input wire clk, + input wire[addr_width-1:0] addr, + output reg [31:0] dread, + input wire[31:0] dwrite, + input wire rw, + input wire valid, + output reg ready +); + parameter addr_width = 8; + + // 4 addresses for each bram + // Selects between current dword and next dword + wire [addr_width-3:0] a0, a1, a2, a3; + assign a0 = (addr[1:0] == 2'b00) ? + addr[addr_width-1:2] : addr[addr_width-1:2] + 1; + assign a1 = (addr[1:0] == 2'b00) || (addr[1:0] == 2'b01) ? + addr[addr_width-1:2] : addr[addr_width-1:2] + 1; + assign a2 = (addr[1:0] == 2'b11) ? + addr[addr_width-1:2] + 1 : addr[addr_width-1:2]; + assign a3 = addr[addr_width-1:2]; + // + // The read buffer shifted over. + // Regarding the ending 2 bits of the address: + // x = read, . = ignore + // a' a'+1 -> where a' = addr[addr_width-1:2] + // 00 [xxxx][....] + // 01 [.xxx][x...] + // 10 [..xx][xx..] + // 11 [...x][xxx.] + // 0123 0123 -> bram# the byte came from + // dbuf will always be in the form of [0123] + // So, an address ending in 11 should be [3012] + // + wire[31:0] dout; + wire[31:0] dbuf, wbuf; + assign dout = + (addr[1:0] == 2'b00) ? { dbuf[31:0] } : + (addr[1:0] == 2'b01) ? { dbuf[23:0], dbuf[31:24] } : + (addr[1:0] == 2'b10) ? { dbuf[15:0], dbuf[31:16] } : + { dbuf[ 7:0], dbuf[31:8] } ; + assign wbuf = + (addr[1:0] == 2'b00) ? { dwrite[31:0] } : + (addr[1:0] == 2'b01) ? { dwrite[ 7:0], dwrite[31:8 ] } : + (addr[1:0] == 2'b10) ? { dwrite[15:0], dwrite[31:16] } : + { dwrite[23:0], dwrite[31:24] } ; + + // Write enable signal + wire we; assign we = valid & rw; + + // FSM (needed?) + reg[1:0] state = 0; + always @(posedge clk) case(state) + 0: begin + if(valid) begin + state <= 1; + end + ready <= 1; + dread <= dout; + end + 1: begin + state <= 0; + ready <= 0; + end + endcase + + sram_1rw1r_32_256_8_sky130 SRAM_0 ( + // MGMT R/W port + .clk0(clk), + .csb0(mgmt_ena[0]), + .web0(mgmt_wen[0]), + .wmask0(mgmt_wen_mask[3:0]), + .addr0(addr), + .din0(dwrite), + .dout0(dread) + ); + + sram_1rw1r_32_256_8_sky130 SRAM_1 ( + // MGMT R/W port + .clk0(mgmt_clk), + .csb0(mgmt_ena[1]), + .web0(mgmt_wen[1]), + .wmask0(mgmt_wen_mask[7:4]), + .addr0(mgmt_addr), + .din0(mgmt_wdata), + .dout0(mgmt_rdata[63:32]) + ); +endmodule +`default_nettype wire
diff --git a/verilog/rtl/hs32_user_proj/hs32_user_core2.v b/verilog/rtl/hs32_user_proj/hs32_user_core2.v index b8b73fd..07a2061 100644 --- a/verilog/rtl/hs32_user_proj/hs32_user_core2.v +++ b/verilog/rtl/hs32_user_proj/hs32_user_core2.v
@@ -1,126 +1,126 @@ -`ifdef verilator - `include "defines.v" - `include "cpu/hs32_cpu.v" - `include "frontend/sram.v" - `include "frontend/mmio.v" -`endif - -`default_nettype none - -module hs32_user_proj ( -`ifdef USE_POWER_PINS - inout vdda1, // User area 1 3.3V supply - inout vdda2, // User area 2 3.3V supply - inout vssa1, // User area 1 analog ground - inout vssa2, // User area 2 analog ground - inout vccd1, // User area 1 1.8V supply - inout vccd2, // User area 2 1.8v supply - inout vssd1, // User area 1 digital ground - inout vssd2, // User area 2 digital ground -`endif - - // Wishbone Slave ports (WB MI A) - input wire wb_clk_i, - input wire wb_rst_i, - input wire wbs_stb_i, - input wire wbs_cyc_i, - input wire wbs_we_i, - input wire [3:0] wbs_sel_i, - input wire [31:0] wbs_dat_i, - input wire [31:0] wbs_adr_i, - output wire wbs_ack_o, - output wire [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input wire [127:0] la_data_in, - output wire [127:0] la_data_out, - input wire [127:0] la_oen, - - // IOs - input wire [`MPRJ_IO_PADS-1:0] io_in, - output wire [`MPRJ_IO_PADS-1:0] io_out, - output wire [`MPRJ_IO_PADS-1:0] io_oeb -); - // Clock and reset - // wire clk = (~la_oen[64])? la_data_in[64] : wb_clk_i; - // wire rst = (~la_oen[65])? la_data_in[65] : wb_rst_i; - wire clk = wb_clk_i; - wire rst = wb_rst_i; - - // Wishbone logic - wire valid; - wire [3:0] wstrb; - assign valid = wbs_cyc_i && wbs_stb_i; - assign wstrb = wbs_sel_i & { 4 { wbs_we_i } }; - // TODO - - // CPU Core 0 Connection - wire[31:0] adr0, dtr0, dtw0, isr0; - wire rw0, val0, rdy0, iack0, irq0, nmi0, usr0, fault0; - wire[23:0] int0; - wire[4:0] vec0; - hs32_cpu #( - .IMUL(1), .BARREL_SHIFTER(1), .PREFETCH_SIZE(3) - ) core0 ( - .i_clk(clk), .reset(rst), - // Mem - .addr(adr0), .rw(rw0), .din(dtr0), .dout(dtw0), - .valid(val0), .ready(rdy0), - // Int - .interrupts(int0), .iack(iack0), .handler(isr0), - .intrq(irq0), .vec(vec0), .nmi(nmi0), - // Misc - .userbit(usr0), .fault(fault0) - ); - - // MMIO - mmio mmio_unit( - .clk(clk), .reset(rst), - // CPU - .valid(val0), .ready(rdy0), - .addr(adr0), .dtw(dtw0), .dtr(dtr0), .rw(rw0), - // SRAM - .sval(svalid), .srdy(sready), - .saddr(saddr), .sdtw(sdtw), .sdtr(sdtr), .srw(srw), - // Interrupt controller - .interrupts(int0), .handler(isr0), .intrq(irq0), - .vec(vec0), .nmi(nmi0) - ); - - // SRAM Controller - wire sready, svalid, srw; - wire [31:0] saddr, sdtw, sdtr; - // Output - wire[15:0] data_in; - wire[15:0] data_out; - wire we, oe, oe_neg, ale0_neg, ale1_neg, bhe, isout; - ext_sram #( - .SRAM_LATCH_LAZY(1) - ) sram ( - .clk(clk), .reset(rst), - // Memory requests - .ready(sready), .valid(svalid), .rw(srw), - .addri(saddr), .dtw(sdtw), .dtr(sdtr), - // External IO interface, active >> HIGH << - .din(data_in), .dout(data_out), - .we(we), .oe(oe), .oe_negedge(oe_neg), - .ale0_negedge(ale0_neg), - .ale1_negedge(ale1_neg), - .bhe(bhe), .isout(isout) - ); - - // SRAM GPIO Logic - assign io_out[36] = usr0; - assign data_in = io_in[35:20]; - assign io_out[35:20] = data_out; - assign io_out[19] = !(oe & oe_neg); - assign io_out[18] = !we; - assign io_out[17] = ale0_neg; - assign io_out[16] = ale1_neg; - assign io_out[15] = !bhe; - - // Output enables - assign io_oeb[36] = 0; - assign io_oeb[35:20] = { (16){ ~isout } }; - assign io_oeb[19:15] = 0; +`ifdef verilator + `include "defines.v" + `include "cpu/hs32_cpu.v" + `include "frontend/sram.v" + `include "frontend/mmio.v" +`endif + +`default_nettype none + +module hs32_user_proj ( +`ifdef USE_POWER_PINS + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground +`endif + + // Wishbone Slave ports (WB MI A) + input wire wb_clk_i, + input wire wb_rst_i, + input wire wbs_stb_i, + input wire wbs_cyc_i, + input wire wbs_we_i, + input wire [3:0] wbs_sel_i, + input wire [31:0] wbs_dat_i, + input wire [31:0] wbs_adr_i, + output wire wbs_ack_o, + output wire [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input wire [127:0] la_data_in, + output wire [127:0] la_data_out, + input wire [127:0] la_oen, + + // IOs + input wire [`MPRJ_IO_PADS-1:0] io_in, + output wire [`MPRJ_IO_PADS-1:0] io_out, + output wire [`MPRJ_IO_PADS-1:0] io_oeb +); + // Clock and reset + // wire clk = (~la_oen[64])? la_data_in[64] : wb_clk_i; + // wire rst = (~la_oen[65])? la_data_in[65] : wb_rst_i; + wire clk = wb_clk_i; + wire rst = wb_rst_i; + + // Wishbone logic + wire valid; + wire [3:0] wstrb; + assign valid = wbs_cyc_i && wbs_stb_i; + assign wstrb = wbs_sel_i & { 4 { wbs_we_i } }; + // TODO + + // CPU Core 0 Connection + wire[31:0] adr0, dtr0, dtw0, isr0; + wire rw0, val0, rdy0, iack0, irq0, nmi0, usr0, fault0; + wire[23:0] int0; + wire[4:0] vec0; + hs32_cpu #( + .IMUL(1), .BARREL_SHIFTER(1), .PREFETCH_SIZE(3) + ) core0 ( + .i_clk(clk), .reset(rst), + // Mem + .addr(adr0), .rw(rw0), .din(dtr0), .dout(dtw0), + .valid(val0), .ready(rdy0), + // Int + .interrupts(int0), .iack(iack0), .handler(isr0), + .intrq(irq0), .vec(vec0), .nmi(nmi0), + // Misc + .userbit(usr0), .fault(fault0) + ); + + // MMIO + mmio mmio_unit( + .clk(clk), .reset(rst), + // CPU + .valid(val0), .ready(rdy0), + .addr(adr0), .dtw(dtw0), .dtr(dtr0), .rw(rw0), + // SRAM + .sval(svalid), .srdy(sready), + .saddr(saddr), .sdtw(sdtw), .sdtr(sdtr), .srw(srw), + // Interrupt controller + .interrupts(int0), .handler(isr0), .intrq(irq0), + .vec(vec0), .nmi(nmi0) + ); + + // SRAM Controller + wire sready, svalid, srw; + wire [31:0] saddr, sdtw, sdtr; + // Output + wire[15:0] data_in; + wire[15:0] data_out; + wire we, oe, oe_neg, ale0_neg, ale1_neg, bhe, isout; + ext_sram #( + .SRAM_LATCH_LAZY(1) + ) sram ( + .clk(clk), .reset(rst), + // Memory requests + .ready(sready), .valid(svalid), .rw(srw), + .addri(saddr), .dtw(sdtw), .dtr(sdtr), + // External IO interface, active >> HIGH << + .din(data_in), .dout(data_out), + .we(we), .oe(oe), .oe_negedge(oe_neg), + .ale0_negedge(ale0_neg), + .ale1_negedge(ale1_neg), + .bhe(bhe), .isout(isout) + ); + + // SRAM GPIO Logic + assign io_out[36] = usr0; + assign data_in = io_in[35:20]; + assign io_out[35:20] = data_out; + assign io_out[19] = !(oe & oe_neg); + assign io_out[18] = !we; + assign io_out[17] = ale0_neg; + assign io_out[16] = ale1_neg; + assign io_out[15] = !bhe; + + // Output enables + assign io_oeb[36] = 0; + assign io_oeb[35:20] = { (16){ ~isout } }; + assign io_oeb[19:15] = 0; endmodule \ No newline at end of file
diff --git a/verilog/rtl/hs32_user_proj/hs32_user_proj.v b/verilog/rtl/hs32_user_proj/hs32_user_proj.v index b8b73fd..07a2061 100644 --- a/verilog/rtl/hs32_user_proj/hs32_user_proj.v +++ b/verilog/rtl/hs32_user_proj/hs32_user_proj.v
@@ -1,126 +1,126 @@ -`ifdef verilator - `include "defines.v" - `include "cpu/hs32_cpu.v" - `include "frontend/sram.v" - `include "frontend/mmio.v" -`endif - -`default_nettype none - -module hs32_user_proj ( -`ifdef USE_POWER_PINS - inout vdda1, // User area 1 3.3V supply - inout vdda2, // User area 2 3.3V supply - inout vssa1, // User area 1 analog ground - inout vssa2, // User area 2 analog ground - inout vccd1, // User area 1 1.8V supply - inout vccd2, // User area 2 1.8v supply - inout vssd1, // User area 1 digital ground - inout vssd2, // User area 2 digital ground -`endif - - // Wishbone Slave ports (WB MI A) - input wire wb_clk_i, - input wire wb_rst_i, - input wire wbs_stb_i, - input wire wbs_cyc_i, - input wire wbs_we_i, - input wire [3:0] wbs_sel_i, - input wire [31:0] wbs_dat_i, - input wire [31:0] wbs_adr_i, - output wire wbs_ack_o, - output wire [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input wire [127:0] la_data_in, - output wire [127:0] la_data_out, - input wire [127:0] la_oen, - - // IOs - input wire [`MPRJ_IO_PADS-1:0] io_in, - output wire [`MPRJ_IO_PADS-1:0] io_out, - output wire [`MPRJ_IO_PADS-1:0] io_oeb -); - // Clock and reset - // wire clk = (~la_oen[64])? la_data_in[64] : wb_clk_i; - // wire rst = (~la_oen[65])? la_data_in[65] : wb_rst_i; - wire clk = wb_clk_i; - wire rst = wb_rst_i; - - // Wishbone logic - wire valid; - wire [3:0] wstrb; - assign valid = wbs_cyc_i && wbs_stb_i; - assign wstrb = wbs_sel_i & { 4 { wbs_we_i } }; - // TODO - - // CPU Core 0 Connection - wire[31:0] adr0, dtr0, dtw0, isr0; - wire rw0, val0, rdy0, iack0, irq0, nmi0, usr0, fault0; - wire[23:0] int0; - wire[4:0] vec0; - hs32_cpu #( - .IMUL(1), .BARREL_SHIFTER(1), .PREFETCH_SIZE(3) - ) core0 ( - .i_clk(clk), .reset(rst), - // Mem - .addr(adr0), .rw(rw0), .din(dtr0), .dout(dtw0), - .valid(val0), .ready(rdy0), - // Int - .interrupts(int0), .iack(iack0), .handler(isr0), - .intrq(irq0), .vec(vec0), .nmi(nmi0), - // Misc - .userbit(usr0), .fault(fault0) - ); - - // MMIO - mmio mmio_unit( - .clk(clk), .reset(rst), - // CPU - .valid(val0), .ready(rdy0), - .addr(adr0), .dtw(dtw0), .dtr(dtr0), .rw(rw0), - // SRAM - .sval(svalid), .srdy(sready), - .saddr(saddr), .sdtw(sdtw), .sdtr(sdtr), .srw(srw), - // Interrupt controller - .interrupts(int0), .handler(isr0), .intrq(irq0), - .vec(vec0), .nmi(nmi0) - ); - - // SRAM Controller - wire sready, svalid, srw; - wire [31:0] saddr, sdtw, sdtr; - // Output - wire[15:0] data_in; - wire[15:0] data_out; - wire we, oe, oe_neg, ale0_neg, ale1_neg, bhe, isout; - ext_sram #( - .SRAM_LATCH_LAZY(1) - ) sram ( - .clk(clk), .reset(rst), - // Memory requests - .ready(sready), .valid(svalid), .rw(srw), - .addri(saddr), .dtw(sdtw), .dtr(sdtr), - // External IO interface, active >> HIGH << - .din(data_in), .dout(data_out), - .we(we), .oe(oe), .oe_negedge(oe_neg), - .ale0_negedge(ale0_neg), - .ale1_negedge(ale1_neg), - .bhe(bhe), .isout(isout) - ); - - // SRAM GPIO Logic - assign io_out[36] = usr0; - assign data_in = io_in[35:20]; - assign io_out[35:20] = data_out; - assign io_out[19] = !(oe & oe_neg); - assign io_out[18] = !we; - assign io_out[17] = ale0_neg; - assign io_out[16] = ale1_neg; - assign io_out[15] = !bhe; - - // Output enables - assign io_oeb[36] = 0; - assign io_oeb[35:20] = { (16){ ~isout } }; - assign io_oeb[19:15] = 0; +`ifdef verilator + `include "defines.v" + `include "cpu/hs32_cpu.v" + `include "frontend/sram.v" + `include "frontend/mmio.v" +`endif + +`default_nettype none + +module hs32_user_proj ( +`ifdef USE_POWER_PINS + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground +`endif + + // Wishbone Slave ports (WB MI A) + input wire wb_clk_i, + input wire wb_rst_i, + input wire wbs_stb_i, + input wire wbs_cyc_i, + input wire wbs_we_i, + input wire [3:0] wbs_sel_i, + input wire [31:0] wbs_dat_i, + input wire [31:0] wbs_adr_i, + output wire wbs_ack_o, + output wire [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input wire [127:0] la_data_in, + output wire [127:0] la_data_out, + input wire [127:0] la_oen, + + // IOs + input wire [`MPRJ_IO_PADS-1:0] io_in, + output wire [`MPRJ_IO_PADS-1:0] io_out, + output wire [`MPRJ_IO_PADS-1:0] io_oeb +); + // Clock and reset + // wire clk = (~la_oen[64])? la_data_in[64] : wb_clk_i; + // wire rst = (~la_oen[65])? la_data_in[65] : wb_rst_i; + wire clk = wb_clk_i; + wire rst = wb_rst_i; + + // Wishbone logic + wire valid; + wire [3:0] wstrb; + assign valid = wbs_cyc_i && wbs_stb_i; + assign wstrb = wbs_sel_i & { 4 { wbs_we_i } }; + // TODO + + // CPU Core 0 Connection + wire[31:0] adr0, dtr0, dtw0, isr0; + wire rw0, val0, rdy0, iack0, irq0, nmi0, usr0, fault0; + wire[23:0] int0; + wire[4:0] vec0; + hs32_cpu #( + .IMUL(1), .BARREL_SHIFTER(1), .PREFETCH_SIZE(3) + ) core0 ( + .i_clk(clk), .reset(rst), + // Mem + .addr(adr0), .rw(rw0), .din(dtr0), .dout(dtw0), + .valid(val0), .ready(rdy0), + // Int + .interrupts(int0), .iack(iack0), .handler(isr0), + .intrq(irq0), .vec(vec0), .nmi(nmi0), + // Misc + .userbit(usr0), .fault(fault0) + ); + + // MMIO + mmio mmio_unit( + .clk(clk), .reset(rst), + // CPU + .valid(val0), .ready(rdy0), + .addr(adr0), .dtw(dtw0), .dtr(dtr0), .rw(rw0), + // SRAM + .sval(svalid), .srdy(sready), + .saddr(saddr), .sdtw(sdtw), .sdtr(sdtr), .srw(srw), + // Interrupt controller + .interrupts(int0), .handler(isr0), .intrq(irq0), + .vec(vec0), .nmi(nmi0) + ); + + // SRAM Controller + wire sready, svalid, srw; + wire [31:0] saddr, sdtw, sdtr; + // Output + wire[15:0] data_in; + wire[15:0] data_out; + wire we, oe, oe_neg, ale0_neg, ale1_neg, bhe, isout; + ext_sram #( + .SRAM_LATCH_LAZY(1) + ) sram ( + .clk(clk), .reset(rst), + // Memory requests + .ready(sready), .valid(svalid), .rw(srw), + .addri(saddr), .dtw(sdtw), .dtr(sdtr), + // External IO interface, active >> HIGH << + .din(data_in), .dout(data_out), + .we(we), .oe(oe), .oe_negedge(oe_neg), + .ale0_negedge(ale0_neg), + .ale1_negedge(ale1_neg), + .bhe(bhe), .isout(isout) + ); + + // SRAM GPIO Logic + assign io_out[36] = usr0; + assign data_in = io_in[35:20]; + assign io_out[35:20] = data_out; + assign io_out[19] = !(oe & oe_neg); + assign io_out[18] = !we; + assign io_out[17] = ale0_neg; + assign io_out[16] = ale1_neg; + assign io_out[15] = !bhe; + + // Output enables + assign io_oeb[36] = 0; + assign io_oeb[35:20] = { (16){ ~isout } }; + assign io_oeb[19:15] = 0; endmodule \ No newline at end of file