Update submodule
diff --git a/verilog/rtl/hs32cpu b/verilog/rtl/hs32cpu index 59961ec..63e3be3 160000 --- a/verilog/rtl/hs32cpu +++ b/verilog/rtl/hs32cpu
@@ -1 +1 @@ -Subproject commit 59961ec3bad9d5d7409151edf3cccd05aeb62f8a +Subproject commit 63e3be34fb9adeb1dfb411f8b6b75598e8d553b0