Updated tests
diff --git a/.gitignore b/.gitignore index d84d2fc..8a6736f 100644 --- a/.gitignore +++ b/.gitignore
@@ -10,3 +10,4 @@ *.out *.out1 *.fst +obj_dir/
diff --git a/verilog/dv/caravel/hs32_soc/assert.v b/verilog/dv/caravel/hs32_soc/assert.v new file mode 100644 index 0000000..a319766 --- /dev/null +++ b/verilog/dv/caravel/hs32_soc/assert.v
@@ -0,0 +1,10 @@ +module assert(input wire clk, input wire test); + always @(posedge clk) + begin + if (test !== 1) + begin + $display("%c[1;31mAssertation failed in %m %c[0m", 27, 27); + $finish_and_return(1); + end + end +endmodule \ No newline at end of file
diff --git a/verilog/dv/caravel/hs32_soc/common.v b/verilog/dv/caravel/hs32_soc/common.v new file mode 100644 index 0000000..59ec0b2 --- /dev/null +++ b/verilog/dv/caravel/hs32_soc/common.v
@@ -0,0 +1,132 @@ + function [0:0] implies; + input [0:0] p, q; + begin + implies = (!p) || q; + end + endfunction + + reg clock; + reg RSTB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + + assign mprj_io_0 = mprj_io[7:0]; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + reg failed = 1; + + initial begin + $dumpfile("tb.vcd"); + $dumpvars(0, tb); + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (25) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end +`ifndef GL_SIM + if(failed) begin + $display("%c[1;31mTest %0d: Failed. %c[0m", 27, TEST_ID, 27); + $finish_and_return(1); + end else begin + $display("%c[1;32mTest %0d: Passed all cases. %c[0m", 27, TEST_ID, 27); + $finish_and_return(0); + end +`endif + $finish; + end + + initial begin + RSTB <= 1'b0; + #1000; + RSTB <= 1'b1; // Release reset + #2000; + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + #200; + power3 <= 1'b1; + #200; + power4 <= 1'b1; + end + +`ifndef GL_SIM + // If fault, then test failed + always @(*) begin + if(tb.uut.mprj.core1.core.EXEC.fault) begin + $display("%c[1;31mTest %0d: Faulted. %c[0m", 27, TEST_ID, 27); + $finish_and_return(1); + end + end +`endif + + always @(mprj_io) begin + #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3 = power1; + wire VDD1V8 = power2; + wire USER_VDD3V3 = power1; + wire USER_VDD1V8 = power2; + wire VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME(FILENAME) + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); \ No newline at end of file
diff --git a/verilog/dv/caravel/hs32_soc/test1/test1_tb.v b/verilog/dv/caravel/hs32_soc/test1/test1_tb.v index ffd6b11..a8c8eae 100644 --- a/verilog/dv/caravel/hs32_soc/test1/test1_tb.v +++ b/verilog/dv/caravel/hs32_soc/test1/test1_tb.v
@@ -8,79 +8,16 @@ `include "caravel.v" `include "spiflash.v" +`include "../assert.v" module tb(); parameter TEST_ID = 1; parameter FILENAME = "test1.hex"; - reg clock; - reg RSTB; - reg power1, power2; - reg power3, power4; - - wire gpio; - wire [37:0] mprj_io; - wire [7:0] mprj_io_0; - - assign mprj_io_0 = mprj_io[7:0]; - - // External clock is used by default. Make this artificially fast for the - // simulation. Normally this would be a slow clock and the digital PLL - // would be the fast clock. - - always #12 clock <= (clock === 1'b0); - - initial begin - clock = 0; - end - - reg failed = 1; - - initial begin - $dumpfile("tb.vcd"); - $dumpvars(0, tb); - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (25) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end -`ifndef GL_SIM - if(failed) begin - $display("%c[1;31m",27); - $display("Test %d: Failed (timed out)!", TEST_ID); - $display("%c[0m",27); - end else begin - $display("%c[1;32m",27); - $display("Test %d: Passed weak cases.", TEST_ID); - $display("%c[0m",27); - end -`endif - $finish; - end - - initial begin - RSTB <= 1'b0; - #1000; - RSTB <= 1'b1; // Release reset - #2000; - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - power3 <= 1'b0; - power4 <= 1'b0; - #200; - power1 <= 1'b1; - #200; - power2 <= 1'b1; - #200; - power3 <= 1'b1; - #200; - power4 <= 1'b1; - end + `include "../common.v" `ifndef GL_SIM + // Weak test cases for debugging initial begin // MOV r0 <- 0xCAFE wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[0] == 32'hCAFE); @@ -89,77 +26,25 @@ // LDR r2 <- [r1+1] wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[2] == 32'hCAFE); failed = 0; + $display("%c[1;32mTest %0d: Passed weak cases. %c[0m", 27, TEST_ID, 27); end - always @(*) begin - if(tb.uut.mprj.core1.core.EXEC.fault) begin - $display("%c[1;31m",27); - $display("Test %d: Faulted!", TEST_ID); - $display("%c[0m",27); - $finish; - end - end + + // Trigger when register write + wire trigger = tb.uut.mprj.core1.core.EXEC.regfile_s.we === 1'b1; + reg[31:0] step = 0; + always @(posedge clock) if(trigger) step <= step + 1; + // Strict assertations for each instruction + assert a0(clock, implies(trigger && step == 0, + tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 0 && + tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'hCAFE)); + assert a1(clock, implies(trigger && step == 1, + tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 1 && + tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'h5)); + assert a2(clock, implies(trigger && step == 2, + tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 2 && + tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'hCAFE)); + assert a3(clock, step <= 3); `endif - - always @(mprj_io) begin - #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); - end - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD3V3 = power1; - wire VDD1V8 = power2; - wire USER_VDD3V3 = power1; - wire USER_VDD1V8 = power2; - wire VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vssio (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (USER_VDD3V3), - .vdda2 (USER_VDD3V3), - .vssa1 (VSS), - .vssa2 (VSS), - .vccd1 (USER_VDD1V8), - .vccd2 (USER_VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - spiflash #( - .FILENAME(FILENAME) - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), // not used - .io3() // not used - ); endmodule + `default_nettype wire - -module assert(input clk, input test); - always @(posedge clk) - begin - if (test !== 1) - begin - $display("ASSERTION FAILED in %m"); - $finish; - end - end -endmodule
diff --git a/verilog/dv/caravel/hs32_soc/test5/README.md b/verilog/dv/caravel/hs32_soc/test5/README.md index 6621deb..ce32cf9 100644 --- a/verilog/dv/caravel/hs32_soc/test5/README.md +++ b/verilog/dv/caravel/hs32_soc/test5/README.md
@@ -2,6 +2,8 @@ **Interrupts and AICT** +# WARNING: Use Test 7 Instead + The HS32 instruction format looks like this: | Type | Wire Format | @@ -16,6 +18,14 @@ | I-Type | `oooo_oooo` | `dddd_mmmm` | `iiii_iiii` | `iiii_iiii` | | R-Type | `oooo_oooo` | `dddd_mmmm` | `nnnn_ssss` | `sDDb_bxxx` | +## Usage + +Use `make` to run test. + +Results should match the *Expected result* listed below. + +Test will display `Passed all cases.` or `Failed.` message indicating errors. + ## Assembly ```assembly @@ -24,11 +34,11 @@ MOV R2, high(COND1) ; 0x5000 MOV R2, R2, 16 ; R2 <- (R2 << 16) -STR R2, R0, 01 ; STR [Rm + imm] <- Rd +STR R2, R0, 0x0010 ; STR [Rm + imm] <- Rd -LDR R3, R0, 0x0010 +LDR R3, R0, 0x0010 ; LDR Rd <- [Rm + imm] -INT +INT 0x0010 ; This is incorrect implementation of interrupts ``` ## Hexadecimal
diff --git a/verilog/dv/caravel/hs32_soc/test5/test5_tb.v b/verilog/dv/caravel/hs32_soc/test5/test5_tb.v index 02e527d..6a1614e 100644 --- a/verilog/dv/caravel/hs32_soc/test5/test5_tb.v +++ b/verilog/dv/caravel/hs32_soc/test5/test5_tb.v
@@ -1,7 +1,9 @@ -`define DBG1 +`ifdef GL_SIM + `define SRAM_LOG_READ + `define SRAM_LOG_WRITE +`endif `default_nettype none - `timescale 1 ns / 1 ns `include "caravel.v" @@ -9,14 +11,22 @@ module tb(); parameter TEST_ID = 5; + parameter FILENAME = "test5.hex"; + + function [0:0] implies; + input [0:0] p, q; + begin + implies = (!p) || q; + end + endfunction reg clock; - reg RSTB; + reg RSTB; reg power1, power2; reg power3, power4; - wire gpio; - wire [37:0] mprj_io; + wire gpio; + wire [37:0] mprj_io; wire [7:0] mprj_io_0; assign mprj_io_0 = mprj_io[7:0]; @@ -31,6 +41,8 @@ clock = 0; end + reg failed = 1; + initial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); @@ -39,16 +51,23 @@ repeat (1000) @(posedge clock); // $display("+1000 cycles"); end - //$display("%c[1;31m",27); - //$display("Test 1: Failed (timed out)!"); - //$display("%c[0m",27); +`ifndef GL_SIM + if(failed) begin + $display("%c[1;31mTest %0d: Failed. %c[0m", 27, TEST_ID, 27); + $finish_and_return(1); + end else begin + $display("%c[1;32mTest %0d: Passed all cases. %c[0m", 27, TEST_ID, 27); + $finish_and_return(0); + end +`endif $finish; end initial begin RSTB <= 1'b0; - #2000; + #1000; RSTB <= 1'b1; // Release reset + #2000; end initial begin // Power-up sequence @@ -66,18 +85,47 @@ power4 <= 1'b1; end +`ifndef GL_SIM + // Weak test cases for debugging initial begin - // Test cases go here + wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[0] == 32'hFF00); + wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[1] == 32'hFF00); + wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[2] == 32'h50000000); + wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[3] == 32'h50000000); + failed = 0; + $display("%c[1;32mTest %0d: Passed weak cases. %c[0m", 27, TEST_ID, 27); end + // Trigger when register write + wire trigger = tb.uut.mprj.core1.core.EXEC.regfile_s.we === 1'b1; + reg[31:0] step = 0; + always @(posedge clock) if(trigger) step <= step + 1; + // Strict assertations for each instruction + assert a0(clock, implies(trigger && step == 0, + tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 0 && + tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'hFF00)); + assert a1(clock, implies(trigger && step == 1, + tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 1 && + tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'hFF00)); + assert a2(clock, implies(trigger && step == 2, + tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 2 && + tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'h5000)); + assert a3(clock, implies(trigger && step == 3, + tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 2 && + tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'h50000000)); + assert a4(clock, implies(trigger && step == 4, + tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 3 && + tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'h50000000)); + assert a5(clock, step <= 5); + + // If fault, then test failed always @(*) begin if(tb.uut.mprj.core1.core.EXEC.fault) begin - $display("%c[1;31m",27); - $display("Test %d: Faulted!", TEST_ID); - $display("%c[0m",27); - $finish; + $display("%c[1;31mTest %0d: Faulted. %c[0m", 27, TEST_ID, 27); + $finish_and_return(1); end end +`endif always @(mprj_io) begin #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); @@ -90,8 +138,8 @@ wire VDD3V3 = power1; wire VDD1V8 = power2; - wire USER_VDD3V3 = power3; - wire USER_VDD1V8 = power4; + wire USER_VDD3V3 = power1; + wire USER_VDD1V8 = power2; wire VSS = 1'b0; caravel uut ( @@ -120,7 +168,7 @@ ); spiflash #( - .FILENAME("test5.hex") + .FILENAME(FILENAME) ) spiflash ( .csb(flash_csb), .clk(flash_clk), @@ -130,4 +178,16 @@ .io3() // not used ); endmodule + +module assert(input clk, input test); + always @(posedge clk) + begin + if (test !== 1) + begin + $display("%c[1;31mAssertation failed in %m %c[0m", 27, 27); + $finish_and_return(1); + end + end +endmodule + `default_nettype wire
diff --git a/verilog/dv/caravel/hs32_soc/test6/README.md b/verilog/dv/caravel/hs32_soc/test6/README.md index 8f52b27..d643669 100644 --- a/verilog/dv/caravel/hs32_soc/test6/README.md +++ b/verilog/dv/caravel/hs32_soc/test6/README.md
@@ -2,6 +2,8 @@ **Branching Test** +# WARNING: Test Incomplete + The HS32 instruction format looks like this: | Type | Wire Format |
diff --git a/verilog/dv/hs32_nocaravel/coretest/Makefile b/verilog/dv/hs32_nocaravel/coretest/Makefile index 7f648a3..02c8d36 100644 --- a/verilog/dv/hs32_nocaravel/coretest/Makefile +++ b/verilog/dv/hs32_nocaravel/coretest/Makefile
@@ -8,7 +8,7 @@ all: ${PATTERN:=.vcd} %.vvp: %_tb.v - iverilog -DSIM -DFUNCTIONAL -I $(RTL_PATH) -I $(RTL_PATH)/hs32cpu \ + iverilog -DSIM -DFUNCTIONAL -D$(TEST) -I $(RTL_PATH) -I $(RTL_PATH)/hs32cpu \ $< -o $@ %.vcd: %.vvp
diff --git a/verilog/dv/hs32_nocaravel/coretest/core_tb.v b/verilog/dv/hs32_nocaravel/coretest/core_tb.v index 3f0143f..223b5db 100644 --- a/verilog/dv/hs32_nocaravel/coretest/core_tb.v +++ b/verilog/dv/hs32_nocaravel/coretest/core_tb.v
@@ -29,7 +29,6 @@ end always #10 wb_clk_i = wb_clk_i === 1'b0; -`define TEST2 `ifdef TEST1 // Default Test localparam NUM_INSTR = 5; @@ -55,21 +54,23 @@ }; `elsif TEST3 // WB test - localparam NUM_INSTR = 15; + localparam NUM_INSTR = 12; // Fake memory access test + // Theoretical penalties @40 MHz: + // < 4k = 0 cycle penalty (* control *) + // > 4k + no HW = +28 cycle penalty (* current method *) + // > 4k + HW, aligned = +6 cycle penalty + // > 4k + HW, misaligned = +12 cycle penalty reg[NUM_INSTR*32-1:0] instr = { { 32'h2400FF00 }, // MOV r0 <- 0xFF00 { 32'h24100021 }, // MOV r1 <- (0x20 | 1) { 32'h34100040 }, // STR [r0+0x40] <- r1 { 32'h24100006 }, // MOV r1 <- 6 { 32'h341000EC }, // STR [r0+0xEC] <- r1 - { 32'h20000800 }, // MOV r0 <- (r0 << 16) - { 32'h10200000 }, // LDR r2 <- [r0] + { 32'h20300800 }, // MOV r3 <- (r0 << 16) + { 32'h10230000 }, // LDR r2 <- [r3] { 32'h50000000 }, // B<0000> 0 - { 32'h24300007 }, // MOV r3 <- 7 { 32'h2440C0DE }, // MOV r4 <- 0xC0DE - { 32'h2450FF00 }, // MOV r5 <- 0xFF00 - { 32'h344500E8 }, // STR [r5+0xE8] <- r4 - { 32'h343500EC }, // STR [r5+0xEC] <- r3 + { 32'h344000E8 }, // STR [r0+0xE8] <- r4 { 32'h64EE0004 }, // SUB lr <- lr - 4 { 32'h5F000000 } // B<1111> 0 (return from interrupt) };
diff --git a/verilog/rtl/hs32_user_proj/dev_wb.v b/verilog/rtl/hs32_user_proj/dev_wb.v index 95e0fca..ffcaae0 100644 --- a/verilog/rtl/hs32_user_proj/dev_wb.v +++ b/verilog/rtl/hs32_user_proj/dev_wb.v
@@ -72,7 +72,10 @@ r_cfg <= 0; end else begin if(we && stb) case(addr) - 2: r_dtr <= dtw; + 2: begin + r_dtr <= dtw; + r_cfg[0] <= r_cfg[2] ? 1 : r_cfg[0]; + end 3: r_cfg <= dtw[2:0]; default: begin end endcase else if(r_cfg[0] && !r_cfg[2]) begin
diff --git a/verilog/rtl/hs32_user_proj/hs32_core1.v b/verilog/rtl/hs32_user_proj/hs32_core1.v index c0c3330..cf758cd 100644 --- a/verilog/rtl/hs32_user_proj/hs32_core1.v +++ b/verilog/rtl/hs32_user_proj/hs32_core1.v
@@ -81,15 +81,22 @@ input wire [31:0] cpu_dtr_e1, // Can't have constants in wrapper - output wire zero, - output wire one, + output wire zero_n, + output wire one_n, + output wire zero_e, + output wire one_e, // Chip enable - output wire ram_ce + output wire ram_ce_n, + output wire ram_ce_e ); // Output constants - assign zero = 1'b0; - assign one = 1'b1; + assign zero_n = 1'b0; + assign zero_e = 1'b0; + assign one_n = 1'b1; + assign one_e = 1'b1; + assign ram_ce_n = ram_ce; + assign ram_ce_e = ram_ce; // Clock and reset // wire clk = (~la_oen[64])? la_data_in[64] : wb_clk_i; @@ -109,7 +116,9 @@ wire iack, fault, userbit; hs32_cpu #( - .IMUL(1), .BARREL_SHIFTER(1), .PREFETCH_SIZE(3) + .IMUL(1), .BARREL_SHIFTER(1), + .PREFETCH_SIZE(3) + ,.LOW_WATER(1) ) core ( .i_clk(clk), .reset(rst), @@ -147,7 +156,7 @@ assign cpu_ack = bus_hold ? 0 : ack; reg ram_bsy; - assign ram_ce = ~(ram_stb | ram_bsy); + wire ram_ce = ~(ram_stb | ram_bsy); always @(posedge clk) if(rst) ram_bsy <= 0; else begin
diff --git a/verilog/rtl/hs32_user_proj/hs32_wrapper.v b/verilog/rtl/hs32_user_proj/hs32_wrapper.v index 5471a4d..373a980 100644 --- a/verilog/rtl/hs32_user_proj/hs32_wrapper.v +++ b/verilog/rtl/hs32_user_proj/hs32_wrapper.v
@@ -21,8 +21,10 @@ `ifdef verilator `include "defines.v" `include "hs32_user_proj/hs32_core1.v" +`ifndef SIM `include "sram_1rw1r_32_256_8_sky130.v" `endif +`endif `ifdef SIM `include "../../macros/bm/sram_1rw1r_32_256_8_sky130.v" @@ -76,9 +78,10 @@ // Independent clock (on independent integer divider) input wire user_clock2 ); - wire zero, one, ce; + wire zero_n, one_n, ce_n; + wire zero_e, one_e, ce_e; - // hs32_core1 core0 (); + assign la_data_out[127:3] = {125{zero_e}}; hs32_core1 core1 ( `ifdef USE_POWER_PINS @@ -135,23 +138,15 @@ .cpu_dtr_e0(dtr_e0), .cpu_dtr_e1(dtr_e1), - // Rx/Tx Buffers - /* - .sr0_dtr(),//sr0_dtr), - .sr1_dtr(),//sr1_dtr), - .sr0_ce(),//sr0_ce), - .sr1_ce(),//sr1_ce), - .srx_addr(),//srx_addr), - .srx_we(),//srx_we), - .srx_dtw(),//srx_dtw), - */ - // Constants - .zero(zero), - .one(one), + .zero_n(zero_n), + .one_n(one_n), + .zero_e(zero_e), + .one_e(one_e), // Chip enable - .ram_ce(ce) + .ram_ce_n(ce_n), + .ram_ce_e(ce_e) ); wire[31:0] sr0_dtr, sr1_dtr, srx_dtw; @@ -168,14 +163,14 @@ .vdd(vccd1), .gnd(vssd1), `endif .clk0(wb_clk_i), - .csb0(ce), + .csb0(ce_n), .web0(wen_n[1]), .wmask0(mask_n[7:4]), .addr0(addr_n[15:8]), .din0({ 4{dtw_n[15:8]} }), .dout0(dtr_n0), // Disabled port - .clk1(zero), .csb1(one), .addr1({8{zero}}), .dout1() + .clk1(zero_n), .csb1(one_n), .addr1({8{zero_n}}), .dout1() ); `SRAM_MODULE sram1( @@ -183,14 +178,14 @@ .vdd(vccd1), .gnd(vssd1), `endif .clk0(wb_clk_i), - .csb0(ce), + .csb0(ce_n), .web0(wen_n[0]), .wmask0(mask_n[3:0]), .addr0(addr_n[7:0]), .din0({ 4{dtw_n[7:0]} }), .dout0(dtr_n1), // Disabled port - .clk1(zero), .csb1(one), .addr1({8{zero}}), .dout1() + .clk1(zero_n), .csb1(one_n), .addr1({8{zero_n}}), .dout1() ); `SRAM_MODULE sram2( @@ -198,14 +193,14 @@ .vdd(vccd1), .gnd(vssd1), `endif .clk0(wb_clk_i), - .csb0(ce), + .csb0(ce_e), .web0(wen_e[1]), .wmask0(mask_e[7:4]), .addr0(addr_e[15:8]), .din0({ 4{dtw_e[15:8]} }), .dout0(dtr_e0), // Disabled port - .clk1(zero), .csb1(one), .addr1({8{zero}}), .dout1() + .clk1(zero_e), .csb1(one_e), .addr1({8{zero_e}}), .dout1() ); `SRAM_MODULE sram3( @@ -213,43 +208,13 @@ .vdd(vccd1), .gnd(vssd1), `endif .clk0(wb_clk_i), - .csb0(ce), + .csb0(ce_e), .web0(wen_e[0]), .wmask0(mask_e[3:0]), .addr0(addr_e[7:0]), .din0({ 4{dtw_e[7:0]} }), .dout0(dtr_e1), // Disabled port - .clk1(zero), .csb1(one), .addr1({8{zero}}), .dout1() + .clk1(zero_e), .csb1(one_e), .addr1({8{zero_e}}), .dout1() ); - - /*`SRAM_MODULE sram4( -`ifdef USE_POWER_PINS - .vdd(vccd1), .gnd(vssd1), -`endif - // Core 1 - .clk0(wb_clk_i), - .csb0(sr0_ce), - .web0(srx_we), - .wmask0({4{ one }}), - .addr0(srx_addr[9:2]), - .din0(srx_dtw), - .dout0(sr0_dtr), - - .clk1(wb_clk_i) - ); - - `SRAM_MODULE sram5( -`ifdef USE_POWER_PINS - .vdd(vccd1), .gnd(vssd1), -`endif - .clk0(wb_clk_i), - - // Core 1 - .clk1(wb_clk_i), - .csb1(sr1_ce), - .addr1(srx_addr[9:2]), - .dout1(sr1_dtr) - );*/ - endmodule // user_project_wrapper