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foss-eda-tools/third_party/shuttle/sky130/mpw-001/slot-008/55ff45bbe7e900d9c326766c75e3222b5efc417a^!/.
commit
55ff45bbe7e900d9c326766c75e3222b5efc417a
[log]
author
Kevin <kevindai02@outlook.com>
Fri Dec 25 17:54:57 2020 -0500
committer
Kevin <kevindai02@outlook.com>
Fri Dec 25 17:54:57 2020 -0500
tree
6dddbbc6986450aea83736d8a7830a6c4ce7b1cc
parent
02bc40947319ae04b1d1a614972b13bf91e8c57a [diff]
Updated top level netlist

diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index ff068f0..403a515 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v

@@ -1,13 +1,353 @@
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
 module user_project_wrapper(user_clock2, wb_clk_i, wb_rst_i, wbs_ack_o, wbs_cyc_i, wbs_stb_i, wbs_we_i, vccd1, vssd1, vccd2, vssd2, vdda1, vssa1, vdda2, vssa2, analog_io, io_in, io_oeb, io_out, la_data_in, la_data_out, la_oen, wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i);
+  wire _NC1;
+  wire _NC10;
+  wire _NC100;
+  wire _NC101;
+  wire _NC102;
+  wire _NC103;
+  wire _NC104;
+  wire _NC105;
+  wire _NC106;
+  wire _NC107;
+  wire _NC108;
+  wire _NC109;
+  wire _NC11;
+  wire _NC110;
+  wire _NC111;
+  wire _NC112;
+  wire _NC113;
+  wire _NC114;
+  wire _NC115;
+  wire _NC116;
+  wire _NC117;
+  wire _NC118;
+  wire _NC119;
+  wire _NC12;
+  wire _NC120;
+  wire _NC121;
+  wire _NC122;
+  wire _NC123;
+  wire _NC124;
+  wire _NC125;
+  wire _NC126;
+  wire _NC127;
+  wire _NC128;
+  wire _NC13;
+  wire _NC14;
+  wire _NC15;
+  wire _NC16;
+  wire _NC17;
+  wire _NC18;
+  wire _NC19;
+  wire _NC2;
+  wire _NC20;
+  wire _NC21;
+  wire _NC22;
+  wire _NC23;
+  wire _NC24;
+  wire _NC25;
+  wire _NC26;
+  wire _NC27;
+  wire _NC28;
+  wire _NC29;
+  wire _NC3;
+  wire _NC30;
+  wire _NC31;
+  wire _NC32;
+  wire _NC33;
+  wire _NC34;
+  wire _NC35;
+  wire _NC36;
+  wire _NC37;
+  wire _NC38;
+  wire _NC39;
+  wire _NC4;
+  wire _NC40;
+  wire _NC41;
+  wire _NC42;
+  wire _NC43;
+  wire _NC44;
+  wire _NC45;
+  wire _NC46;
+  wire _NC47;
+  wire _NC48;
+  wire _NC49;
+  wire _NC5;
+  wire _NC50;
+  wire _NC51;
+  wire _NC52;
+  wire _NC53;
+  wire _NC54;
+  wire _NC55;
+  wire _NC56;
+  wire _NC57;
+  wire _NC58;
+  wire _NC59;
+  wire _NC6;
+  wire _NC60;
+  wire _NC61;
+  wire _NC62;
+  wire _NC63;
+  wire _NC64;
+  wire _NC65;
+  wire _NC66;
+  wire _NC67;
+  wire _NC68;
+  wire _NC69;
+  wire _NC7;
+  wire _NC70;
+  wire _NC71;
+  wire _NC72;
+  wire _NC73;
+  wire _NC74;
+  wire _NC75;
+  wire _NC76;
+  wire _NC77;
+  wire _NC78;
+  wire _NC79;
+  wire _NC8;
+  wire _NC80;
+  wire _NC81;
+  wire _NC82;
+  wire _NC83;
+  wire _NC84;
+  wire _NC85;
+  wire _NC86;
+  wire _NC87;
+  wire _NC88;
+  wire _NC89;
+  wire _NC9;
+  wire _NC90;
+  wire _NC91;
+  wire _NC92;
+  wire _NC93;
+  wire _NC94;
+  wire _NC95;
+  wire _NC96;
+  wire _NC97;
+  wire _NC98;
+  wire _NC99;
+  wire \addr_e[0] ;
+  wire \addr_e[10] ;
+  wire \addr_e[11] ;
+  wire \addr_e[12] ;
+  wire \addr_e[13] ;
+  wire \addr_e[14] ;
+  wire \addr_e[15] ;
+  wire \addr_e[1] ;
+  wire \addr_e[2] ;
+  wire \addr_e[3] ;
+  wire \addr_e[4] ;
+  wire \addr_e[5] ;
+  wire \addr_e[6] ;
+  wire \addr_e[7] ;
+  wire \addr_e[8] ;
+  wire \addr_e[9] ;
+  wire \addr_n[0] ;
+  wire \addr_n[10] ;
+  wire \addr_n[11] ;
+  wire \addr_n[12] ;
+  wire \addr_n[13] ;
+  wire \addr_n[14] ;
+  wire \addr_n[15] ;
+  wire \addr_n[1] ;
+  wire \addr_n[2] ;
+  wire \addr_n[3] ;
+  wire \addr_n[4] ;
+  wire \addr_n[5] ;
+  wire \addr_n[6] ;
+  wire \addr_n[7] ;
+  wire \addr_n[8] ;
+  wire \addr_n[9] ;
   inout [30:0] analog_io;
+  wire ce_e;
+  wire ce_n;
+  wire \dtr_e0[0] ;
+  wire \dtr_e0[10] ;
+  wire \dtr_e0[11] ;
+  wire \dtr_e0[12] ;
+  wire \dtr_e0[13] ;
+  wire \dtr_e0[14] ;
+  wire \dtr_e0[15] ;
+  wire \dtr_e0[16] ;
+  wire \dtr_e0[17] ;
+  wire \dtr_e0[18] ;
+  wire \dtr_e0[19] ;
+  wire \dtr_e0[1] ;
+  wire \dtr_e0[20] ;
+  wire \dtr_e0[21] ;
+  wire \dtr_e0[22] ;
+  wire \dtr_e0[23] ;
+  wire \dtr_e0[24] ;
+  wire \dtr_e0[25] ;
+  wire \dtr_e0[26] ;
+  wire \dtr_e0[27] ;
+  wire \dtr_e0[28] ;
+  wire \dtr_e0[29] ;
+  wire \dtr_e0[2] ;
+  wire \dtr_e0[30] ;
+  wire \dtr_e0[31] ;
+  wire \dtr_e0[3] ;
+  wire \dtr_e0[4] ;
+  wire \dtr_e0[5] ;
+  wire \dtr_e0[6] ;
+  wire \dtr_e0[7] ;
+  wire \dtr_e0[8] ;
+  wire \dtr_e0[9] ;
+  wire \dtr_e1[0] ;
+  wire \dtr_e1[10] ;
+  wire \dtr_e1[11] ;
+  wire \dtr_e1[12] ;
+  wire \dtr_e1[13] ;
+  wire \dtr_e1[14] ;
+  wire \dtr_e1[15] ;
+  wire \dtr_e1[16] ;
+  wire \dtr_e1[17] ;
+  wire \dtr_e1[18] ;
+  wire \dtr_e1[19] ;
+  wire \dtr_e1[1] ;
+  wire \dtr_e1[20] ;
+  wire \dtr_e1[21] ;
+  wire \dtr_e1[22] ;
+  wire \dtr_e1[23] ;
+  wire \dtr_e1[24] ;
+  wire \dtr_e1[25] ;
+  wire \dtr_e1[26] ;
+  wire \dtr_e1[27] ;
+  wire \dtr_e1[28] ;
+  wire \dtr_e1[29] ;
+  wire \dtr_e1[2] ;
+  wire \dtr_e1[30] ;
+  wire \dtr_e1[31] ;
+  wire \dtr_e1[3] ;
+  wire \dtr_e1[4] ;
+  wire \dtr_e1[5] ;
+  wire \dtr_e1[6] ;
+  wire \dtr_e1[7] ;
+  wire \dtr_e1[8] ;
+  wire \dtr_e1[9] ;
+  wire \dtr_n0[0] ;
+  wire \dtr_n0[10] ;
+  wire \dtr_n0[11] ;
+  wire \dtr_n0[12] ;
+  wire \dtr_n0[13] ;
+  wire \dtr_n0[14] ;
+  wire \dtr_n0[15] ;
+  wire \dtr_n0[16] ;
+  wire \dtr_n0[17] ;
+  wire \dtr_n0[18] ;
+  wire \dtr_n0[19] ;
+  wire \dtr_n0[1] ;
+  wire \dtr_n0[20] ;
+  wire \dtr_n0[21] ;
+  wire \dtr_n0[22] ;
+  wire \dtr_n0[23] ;
+  wire \dtr_n0[24] ;
+  wire \dtr_n0[25] ;
+  wire \dtr_n0[26] ;
+  wire \dtr_n0[27] ;
+  wire \dtr_n0[28] ;
+  wire \dtr_n0[29] ;
+  wire \dtr_n0[2] ;
+  wire \dtr_n0[30] ;
+  wire \dtr_n0[31] ;
+  wire \dtr_n0[3] ;
+  wire \dtr_n0[4] ;
+  wire \dtr_n0[5] ;
+  wire \dtr_n0[6] ;
+  wire \dtr_n0[7] ;
+  wire \dtr_n0[8] ;
+  wire \dtr_n0[9] ;
+  wire \dtr_n1[0] ;
+  wire \dtr_n1[10] ;
+  wire \dtr_n1[11] ;
+  wire \dtr_n1[12] ;
+  wire \dtr_n1[13] ;
+  wire \dtr_n1[14] ;
+  wire \dtr_n1[15] ;
+  wire \dtr_n1[16] ;
+  wire \dtr_n1[17] ;
+  wire \dtr_n1[18] ;
+  wire \dtr_n1[19] ;
+  wire \dtr_n1[1] ;
+  wire \dtr_n1[20] ;
+  wire \dtr_n1[21] ;
+  wire \dtr_n1[22] ;
+  wire \dtr_n1[23] ;
+  wire \dtr_n1[24] ;
+  wire \dtr_n1[25] ;
+  wire \dtr_n1[26] ;
+  wire \dtr_n1[27] ;
+  wire \dtr_n1[28] ;
+  wire \dtr_n1[29] ;
+  wire \dtr_n1[2] ;
+  wire \dtr_n1[30] ;
+  wire \dtr_n1[31] ;
+  wire \dtr_n1[3] ;
+  wire \dtr_n1[4] ;
+  wire \dtr_n1[5] ;
+  wire \dtr_n1[6] ;
+  wire \dtr_n1[7] ;
+  wire \dtr_n1[8] ;
+  wire \dtr_n1[9] ;
+  wire \dtw_e[0] ;
+  wire \dtw_e[10] ;
+  wire \dtw_e[11] ;
+  wire \dtw_e[12] ;
+  wire \dtw_e[13] ;
+  wire \dtw_e[14] ;
+  wire \dtw_e[15] ;
+  wire \dtw_e[1] ;
+  wire \dtw_e[2] ;
+  wire \dtw_e[3] ;
+  wire \dtw_e[4] ;
+  wire \dtw_e[5] ;
+  wire \dtw_e[6] ;
+  wire \dtw_e[7] ;
+  wire \dtw_e[8] ;
+  wire \dtw_e[9] ;
+  wire \dtw_n[0] ;
+  wire \dtw_n[10] ;
+  wire \dtw_n[11] ;
+  wire \dtw_n[12] ;
+  wire \dtw_n[13] ;
+  wire \dtw_n[14] ;
+  wire \dtw_n[15] ;
+  wire \dtw_n[1] ;
+  wire \dtw_n[2] ;
+  wire \dtw_n[3] ;
+  wire \dtw_n[4] ;
+  wire \dtw_n[5] ;
+  wire \dtw_n[6] ;
+  wire \dtw_n[7] ;
+  wire \dtw_n[8] ;
+  wire \dtw_n[9] ;
   input [37:0] io_in;
   output [37:0] io_oeb;
   output [37:0] io_out;
   input [127:0] la_data_in;
   output [127:0] la_data_out;
   input [127:0] la_oen;
+  wire \mask_e[0] ;
+  wire \mask_e[1] ;
+  wire \mask_e[2] ;
+  wire \mask_e[3] ;
+  wire \mask_e[4] ;
+  wire \mask_e[5] ;
+  wire \mask_e[6] ;
+  wire \mask_e[7] ;
+  wire \mask_n[0] ;
+  wire \mask_n[1] ;
+  wire \mask_n[2] ;
+  wire \mask_n[3] ;
+  wire \mask_n[4] ;
+  wire \mask_n[5] ;
+  wire \mask_n[6] ;
+  wire \mask_n[7] ;
+  wire one_e;
+  wire one_n;
   input user_clock2;
   input vccd1;
   input vccd2;
@@ -27,21 +367,37 @@
   input [3:0] wbs_sel_i;
   input wbs_stb_i;
   input wbs_we_i;
-  user_proj_example mprj (
+  wire \wen_e[0] ;
+  wire \wen_e[1] ;
+  wire \wen_n[0] ;
+  wire \wen_n[1] ;
+  wire zero_e;
+  wire zero_n;
+  hs32_core1 core1 (
+    .VGND(vssd1),
+    .VPWR(vccd1),
+    .cpu_addr_e({ \addr_e[15] , \addr_e[14] , \addr_e[13] , \addr_e[12] , \addr_e[11] , \addr_e[10] , \addr_e[9] , \addr_e[8] , \addr_e[7] , \addr_e[6] , \addr_e[5] , \addr_e[4] , \addr_e[3] , \addr_e[2] , \addr_e[1] , \addr_e[0]  }),
+    .cpu_addr_n({ \addr_n[15] , \addr_n[14] , \addr_n[13] , \addr_n[12] , \addr_n[11] , \addr_n[10] , \addr_n[9] , \addr_n[8] , \addr_n[7] , \addr_n[6] , \addr_n[5] , \addr_n[4] , \addr_n[3] , \addr_n[2] , \addr_n[1] , \addr_n[0]  }),
+    .cpu_dtr_e0({ \dtr_e0[31] , \dtr_e0[30] , \dtr_e0[29] , \dtr_e0[28] , \dtr_e0[27] , \dtr_e0[26] , \dtr_e0[25] , \dtr_e0[24] , \dtr_e0[23] , \dtr_e0[22] , \dtr_e0[21] , \dtr_e0[20] , \dtr_e0[19] , \dtr_e0[18] , \dtr_e0[17] , \dtr_e0[16] , \dtr_e0[15] , \dtr_e0[14] , \dtr_e0[13] , \dtr_e0[12] , \dtr_e0[11] , \dtr_e0[10] , \dtr_e0[9] , \dtr_e0[8] , \dtr_e0[7] , \dtr_e0[6] , \dtr_e0[5] , \dtr_e0[4] , \dtr_e0[3] , \dtr_e0[2] , \dtr_e0[1] , \dtr_e0[0]  }),
+    .cpu_dtr_e1({ \dtr_e1[31] , \dtr_e1[30] , \dtr_e1[29] , \dtr_e1[28] , \dtr_e1[27] , \dtr_e1[26] , \dtr_e1[25] , \dtr_e1[24] , \dtr_e1[23] , \dtr_e1[22] , \dtr_e1[21] , \dtr_e1[20] , \dtr_e1[19] , \dtr_e1[18] , \dtr_e1[17] , \dtr_e1[16] , \dtr_e1[15] , \dtr_e1[14] , \dtr_e1[13] , \dtr_e1[12] , \dtr_e1[11] , \dtr_e1[10] , \dtr_e1[9] , \dtr_e1[8] , \dtr_e1[7] , \dtr_e1[6] , \dtr_e1[5] , \dtr_e1[4] , \dtr_e1[3] , \dtr_e1[2] , \dtr_e1[1] , \dtr_e1[0]  }),
+    .cpu_dtr_n0({ \dtr_n0[31] , \dtr_n0[30] , \dtr_n0[29] , \dtr_n0[28] , \dtr_n0[27] , \dtr_n0[26] , \dtr_n0[25] , \dtr_n0[24] , \dtr_n0[23] , \dtr_n0[22] , \dtr_n0[21] , \dtr_n0[20] , \dtr_n0[19] , \dtr_n0[18] , \dtr_n0[17] , \dtr_n0[16] , \dtr_n0[15] , \dtr_n0[14] , \dtr_n0[13] , \dtr_n0[12] , \dtr_n0[11] , \dtr_n0[10] , \dtr_n0[9] , \dtr_n0[8] , \dtr_n0[7] , \dtr_n0[6] , \dtr_n0[5] , \dtr_n0[4] , \dtr_n0[3] , \dtr_n0[2] , \dtr_n0[1] , \dtr_n0[0]  }),
+    .cpu_dtr_n1({ \dtr_n1[31] , \dtr_n1[30] , \dtr_n1[29] , \dtr_n1[28] , \dtr_n1[27] , \dtr_n1[26] , \dtr_n1[25] , \dtr_n1[24] , \dtr_n1[23] , \dtr_n1[22] , \dtr_n1[21] , \dtr_n1[20] , \dtr_n1[19] , \dtr_n1[18] , \dtr_n1[17] , \dtr_n1[16] , \dtr_n1[15] , \dtr_n1[14] , \dtr_n1[13] , \dtr_n1[12] , \dtr_n1[11] , \dtr_n1[10] , \dtr_n1[9] , \dtr_n1[8] , \dtr_n1[7] , \dtr_n1[6] , \dtr_n1[5] , \dtr_n1[4] , \dtr_n1[3] , \dtr_n1[2] , \dtr_n1[1] , \dtr_n1[0]  }),
+    .cpu_dtw_e({ \dtw_e[15] , \dtw_e[14] , \dtw_e[13] , \dtw_e[12] , \dtw_e[11] , \dtw_e[10] , \dtw_e[9] , \dtw_e[8] , \dtw_e[7] , \dtw_e[6] , \dtw_e[5] , \dtw_e[4] , \dtw_e[3] , \dtw_e[2] , \dtw_e[1] , \dtw_e[0]  }),
+    .cpu_dtw_n({ \dtw_n[15] , \dtw_n[14] , \dtw_n[13] , \dtw_n[12] , \dtw_n[11] , \dtw_n[10] , \dtw_n[9] , \dtw_n[8] , \dtw_n[7] , \dtw_n[6] , \dtw_n[5] , \dtw_n[4] , \dtw_n[3] , \dtw_n[2] , \dtw_n[1] , \dtw_n[0]  }),
+    .cpu_mask_e({ \mask_e[7] , \mask_e[6] , \mask_e[5] , \mask_e[4] , \mask_e[3] , \mask_e[2] , \mask_e[1] , \mask_e[0]  }),
+    .cpu_mask_n({ \mask_n[7] , \mask_n[6] , \mask_n[5] , \mask_n[4] , \mask_n[3] , \mask_n[2] , \mask_n[1] , \mask_n[0]  }),
+    .cpu_wen_e({ \wen_e[1] , \wen_e[0]  }),
+    .cpu_wen_n({ \wen_n[1] , \wen_n[0]  }),
     .io_in(io_in),
     .io_oeb(io_oeb),
     .io_out(io_out),
-    .la_data_in(la_data_in),
-    .la_data_out(la_data_out),
-    .la_oen(la_oen),
-    .vccd1(vccd1),
-    .vccd2(vccd2),
-    .vdda1(vdda1),
-    .vdda2(vdda2),
-    .vssa1(vssa1),
-    .vssa2(vssa2),
-    .vssd1(vssd1),
-    .vssd2(vssd2),
+    .la_data_in(la_data_in[1:0]),
+    .la_data_out(la_data_out[2:0]),
+    .la_oen(la_oen[1:0]),
+    .one_e(one_e),
+    .one_n(one_n),
+    .ram_ce_e(ce_e),
+    .ram_ce_n(ce_n),
     .wb_clk_i(wb_clk_i),
     .wb_rst_i(wb_rst_i),
     .wbs_ack_o(wbs_ack_o),
@@ -51,6 +407,68 @@
     .wbs_dat_o(wbs_dat_o),
     .wbs_sel_i(wbs_sel_i),
     .wbs_stb_i(wbs_stb_i),
-    .wbs_we_i(wbs_we_i)
+    .wbs_we_i(wbs_we_i),
+    .zero_e(zero_e),
+    .zero_n(zero_n)
+  );
+  sram_1rw1r_32_256_8_sky130 sram0 (
+    .addr0({ \addr_n[15] , \addr_n[14] , \addr_n[13] , \addr_n[12] , \addr_n[11] , \addr_n[10] , \addr_n[9] , \addr_n[8]  }),
+    .addr1({ zero_n, zero_n, zero_n, zero_n, zero_n, zero_n, zero_n, zero_n }),
+    .clk0(wb_clk_i),
+    .clk1(zero_n),
+    .csb0(ce_n),
+    .csb1(one_n),
+    .din0({ \dtw_n[15] , \dtw_n[14] , \dtw_n[13] , \dtw_n[12] , \dtw_n[11] , \dtw_n[10] , \dtw_n[9] , \dtw_n[8] , \dtw_n[15] , \dtw_n[14] , \dtw_n[13] , \dtw_n[12] , \dtw_n[11] , \dtw_n[10] , \dtw_n[9] , \dtw_n[8] , \dtw_n[15] , \dtw_n[14] , \dtw_n[13] , \dtw_n[12] , \dtw_n[11] , \dtw_n[10] , \dtw_n[9] , \dtw_n[8] , \dtw_n[15] , \dtw_n[14] , \dtw_n[13] , \dtw_n[12] , \dtw_n[11] , \dtw_n[10] , \dtw_n[9] , \dtw_n[8]  }),
+    .dout0({ \dtr_n0[31] , \dtr_n0[30] , \dtr_n0[29] , \dtr_n0[28] , \dtr_n0[27] , \dtr_n0[26] , \dtr_n0[25] , \dtr_n0[24] , \dtr_n0[23] , \dtr_n0[22] , \dtr_n0[21] , \dtr_n0[20] , \dtr_n0[19] , \dtr_n0[18] , \dtr_n0[17] , \dtr_n0[16] , \dtr_n0[15] , \dtr_n0[14] , \dtr_n0[13] , \dtr_n0[12] , \dtr_n0[11] , \dtr_n0[10] , \dtr_n0[9] , \dtr_n0[8] , \dtr_n0[7] , \dtr_n0[6] , \dtr_n0[5] , \dtr_n0[4] , \dtr_n0[3] , \dtr_n0[2] , \dtr_n0[1] , \dtr_n0[0]  }),
+    .dout1({ _NC1, _NC2, _NC3, _NC4, _NC5, _NC6, _NC7, _NC8, _NC9, _NC10, _NC11, _NC12, _NC13, _NC14, _NC15, _NC16, _NC17, _NC18, _NC19, _NC20, _NC21, _NC22, _NC23, _NC24, _NC25, _NC26, _NC27, _NC28, _NC29, _NC30, _NC31, _NC32 }),
+    .gnd(vssd1),
+    .vdd(vccd1),
+    .web0(\wen_n[1] ),
+    .wmask0({ \mask_n[7] , \mask_n[6] , \mask_n[5] , \mask_n[4]  })
+  );
+  sram_1rw1r_32_256_8_sky130 sram1 (
+    .addr0({ \addr_n[7] , \addr_n[6] , \addr_n[5] , \addr_n[4] , \addr_n[3] , \addr_n[2] , \addr_n[1] , \addr_n[0]  }),
+    .addr1({ zero_n, zero_n, zero_n, zero_n, zero_n, zero_n, zero_n, zero_n }),
+    .clk0(wb_clk_i),
+    .clk1(zero_n),
+    .csb0(ce_n),
+    .csb1(one_n),
+    .din0({ \dtw_n[7] , \dtw_n[6] , \dtw_n[5] , \dtw_n[4] , \dtw_n[3] , \dtw_n[2] , \dtw_n[1] , \dtw_n[0] , \dtw_n[7] , \dtw_n[6] , \dtw_n[5] , \dtw_n[4] , \dtw_n[3] , \dtw_n[2] , \dtw_n[1] , \dtw_n[0] , \dtw_n[7] , \dtw_n[6] , \dtw_n[5] , \dtw_n[4] , \dtw_n[3] , \dtw_n[2] , \dtw_n[1] , \dtw_n[0] , \dtw_n[7] , \dtw_n[6] , \dtw_n[5] , \dtw_n[4] , \dtw_n[3] , \dtw_n[2] , \dtw_n[1] , \dtw_n[0]  }),
+    .dout0({ \dtr_n1[31] , \dtr_n1[30] , \dtr_n1[29] , \dtr_n1[28] , \dtr_n1[27] , \dtr_n1[26] , \dtr_n1[25] , \dtr_n1[24] , \dtr_n1[23] , \dtr_n1[22] , \dtr_n1[21] , \dtr_n1[20] , \dtr_n1[19] , \dtr_n1[18] , \dtr_n1[17] , \dtr_n1[16] , \dtr_n1[15] , \dtr_n1[14] , \dtr_n1[13] , \dtr_n1[12] , \dtr_n1[11] , \dtr_n1[10] , \dtr_n1[9] , \dtr_n1[8] , \dtr_n1[7] , \dtr_n1[6] , \dtr_n1[5] , \dtr_n1[4] , \dtr_n1[3] , \dtr_n1[2] , \dtr_n1[1] , \dtr_n1[0]  }),
+    .dout1({ _NC33, _NC34, _NC35, _NC36, _NC37, _NC38, _NC39, _NC40, _NC41, _NC42, _NC43, _NC44, _NC45, _NC46, _NC47, _NC48, _NC49, _NC50, _NC51, _NC52, _NC53, _NC54, _NC55, _NC56, _NC57, _NC58, _NC59, _NC60, _NC61, _NC62, _NC63, _NC64 }),
+    .gnd(vssd1),
+    .vdd(vccd1),
+    .web0(\wen_n[0] ),
+    .wmask0({ \mask_n[3] , \mask_n[2] , \mask_n[1] , \mask_n[0]  })
+  );
+  sram_1rw1r_32_256_8_sky130 sram2 (
+    .addr0({ \addr_e[15] , \addr_e[14] , \addr_e[13] , \addr_e[12] , \addr_e[11] , \addr_e[10] , \addr_e[9] , \addr_e[8]  }),
+    .addr1({ zero_e, zero_e, zero_e, zero_e, zero_e, zero_e, zero_e, zero_e }),
+    .clk0(wb_clk_i),
+    .clk1(zero_e),
+    .csb0(ce_e),
+    .csb1(one_e),
+    .din0({ \dtw_e[15] , \dtw_e[14] , \dtw_e[13] , \dtw_e[12] , \dtw_e[11] , \dtw_e[10] , \dtw_e[9] , \dtw_e[8] , \dtw_e[15] , \dtw_e[14] , \dtw_e[13] , \dtw_e[12] , \dtw_e[11] , \dtw_e[10] , \dtw_e[9] , \dtw_e[8] , \dtw_e[15] , \dtw_e[14] , \dtw_e[13] , \dtw_e[12] , \dtw_e[11] , \dtw_e[10] , \dtw_e[9] , \dtw_e[8] , \dtw_e[15] , \dtw_e[14] , \dtw_e[13] , \dtw_e[12] , \dtw_e[11] , \dtw_e[10] , \dtw_e[9] , \dtw_e[8]  }),
+    .dout0({ \dtr_e0[31] , \dtr_e0[30] , \dtr_e0[29] , \dtr_e0[28] , \dtr_e0[27] , \dtr_e0[26] , \dtr_e0[25] , \dtr_e0[24] , \dtr_e0[23] , \dtr_e0[22] , \dtr_e0[21] , \dtr_e0[20] , \dtr_e0[19] , \dtr_e0[18] , \dtr_e0[17] , \dtr_e0[16] , \dtr_e0[15] , \dtr_e0[14] , \dtr_e0[13] , \dtr_e0[12] , \dtr_e0[11] , \dtr_e0[10] , \dtr_e0[9] , \dtr_e0[8] , \dtr_e0[7] , \dtr_e0[6] , \dtr_e0[5] , \dtr_e0[4] , \dtr_e0[3] , \dtr_e0[2] , \dtr_e0[1] , \dtr_e0[0]  }),
+    .dout1({ _NC65, _NC66, _NC67, _NC68, _NC69, _NC70, _NC71, _NC72, _NC73, _NC74, _NC75, _NC76, _NC77, _NC78, _NC79, _NC80, _NC81, _NC82, _NC83, _NC84, _NC85, _NC86, _NC87, _NC88, _NC89, _NC90, _NC91, _NC92, _NC93, _NC94, _NC95, _NC96 }),
+    .gnd(vssd1),
+    .vdd(vccd1),
+    .web0(\wen_e[1] ),
+    .wmask0({ \mask_e[7] , \mask_e[6] , \mask_e[5] , \mask_e[4]  })
+  );
+  sram_1rw1r_32_256_8_sky130 sram3 (
+    .addr0({ \addr_e[7] , \addr_e[6] , \addr_e[5] , \addr_e[4] , \addr_e[3] , \addr_e[2] , \addr_e[1] , \addr_e[0]  }),
+    .addr1({ zero_e, zero_e, zero_e, zero_e, zero_e, zero_e, zero_e, zero_e }),
+    .clk0(wb_clk_i),
+    .clk1(zero_e),
+    .csb0(ce_e),
+    .csb1(one_e),
+    .din0({ \dtw_e[7] , \dtw_e[6] , \dtw_e[5] , \dtw_e[4] , \dtw_e[3] , \dtw_e[2] , \dtw_e[1] , \dtw_e[0] , \dtw_e[7] , \dtw_e[6] , \dtw_e[5] , \dtw_e[4] , \dtw_e[3] , \dtw_e[2] , \dtw_e[1] , \dtw_e[0] , \dtw_e[7] , \dtw_e[6] , \dtw_e[5] , \dtw_e[4] , \dtw_e[3] , \dtw_e[2] , \dtw_e[1] , \dtw_e[0] , \dtw_e[7] , \dtw_e[6] , \dtw_e[5] , \dtw_e[4] , \dtw_e[3] , \dtw_e[2] , \dtw_e[1] , \dtw_e[0]  }),
+    .dout0({ \dtr_e1[31] , \dtr_e1[30] , \dtr_e1[29] , \dtr_e1[28] , \dtr_e1[27] , \dtr_e1[26] , \dtr_e1[25] , \dtr_e1[24] , \dtr_e1[23] , \dtr_e1[22] , \dtr_e1[21] , \dtr_e1[20] , \dtr_e1[19] , \dtr_e1[18] , \dtr_e1[17] , \dtr_e1[16] , \dtr_e1[15] , \dtr_e1[14] , \dtr_e1[13] , \dtr_e1[12] , \dtr_e1[11] , \dtr_e1[10] , \dtr_e1[9] , \dtr_e1[8] , \dtr_e1[7] , \dtr_e1[6] , \dtr_e1[5] , \dtr_e1[4] , \dtr_e1[3] , \dtr_e1[2] , \dtr_e1[1] , \dtr_e1[0]  }),
+    .dout1({ _NC97, _NC98, _NC99, _NC100, _NC101, _NC102, _NC103, _NC104, _NC105, _NC106, _NC107, _NC108, _NC109, _NC110, _NC111, _NC112, _NC113, _NC114, _NC115, _NC116, _NC117, _NC118, _NC119, _NC120, _NC121, _NC122, _NC123, _NC124, _NC125, _NC126, _NC127, _NC128 }),
+    .gnd(vssd1),
+    .vdd(vccd1),
+    .web0(\wen_e[0] ),
+    .wmask0({ \mask_e[3] , \mask_e[2] , \mask_e[1] , \mask_e[0]  })
   );
 endmodule