Added images/ and sram
diff --git a/images/CPU-Overview.png b/images/CPU-Overview.png new file mode 100644 index 0000000..4251cbe --- /dev/null +++ b/images/CPU-Overview.png Binary files differ
diff --git a/images/Execution-Overview.png b/images/Execution-Overview.png new file mode 100644 index 0000000..8456ba2 --- /dev/null +++ b/images/Execution-Overview.png Binary files differ
diff --git a/images/cpu-block.svg b/images/cpu-block.svg new file mode 100644 index 0000000..4bf2a3a --- /dev/null +++ b/images/cpu-block.svg
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Each chip is selected by the upper address bits, thus forming "banks" in memory space.</p><p>The specific implementation is up to the wiring and programmer to account for the memory topography. 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refY="0" orient="auto"><path d="M0 -4 -11 0 0 4z"/></marker></defs><g id="waves_0"><g id="lanes_0" transform="translate(80.5, 46.5)"><g id="gmarks_0"><g style="stroke:#888;stroke-width:0.5;stroke-dasharray:1,3"><line id="gmark_0_0" x1="0" y1="0" x2="0" y2="210"/><line id="gmark_1_0" x1="40" y1="0" x2="40" y2="210"/><line id="gmark_2_0" x1="80" y1="0" x2="80" y2="210"/><line id="gmark_3_0" x1="120" y1="0" x2="120" y2="210"/><line id="gmark_4_0" x1="160" y1="0" x2="160" y2="210"/><line id="gmark_5_0" x1="200" y1="0" x2="200" y2="210"/><line id="gmark_6_0" x1="240" y1="0" x2="240" y2="210"/><line id="gmark_7_0" x1="280" y1="0" x2="280" y2="210"/><line id="gmark_8_0" x1="320" y1="0" x2="320" y2="210"/><line id="gmark_9_0" x1="360" y1="0" x2="360" y2="210"/><line id="gmark_10_0" x1="400" y1="0" x2="400" y2="210"/><line id="gmark_11_0" x1="440" y1="0" x2="440" y2="210"/></g><text x="220" y="-13" fill="#000" text-anchor="middle" xml:space="preserve"><tspan>Figure 1. Read Cycle Timing Waveform</tspan></text></g><g id="wavelane_0_0" transform="translate(0,5)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>CLK</tspan></text><g id="wavelane_draw_0_0" transform="translate(0, 0)"><use xlink:href="#111" transform="translate(0)"/><use xlink:href="#111" transform="translate(20)"/><use xlink:href="#nclk" transform="translate(40)"/><use xlink:href="#000" transform="translate(60)"/><use xlink:href="#pclk" transform="translate(80)"/><use xlink:href="#111" transform="translate(100)"/><use xlink:href="#nclk" transform="translate(120)"/><use xlink:href="#000" transform="translate(140)"/><use xlink:href="#pclk" transform="translate(160)"/><use xlink:href="#111" transform="translate(180)"/><use xlink:href="#nclk" transform="translate(200)"/><use xlink:href="#000" transform="translate(220)"/><use xlink:href="#pclk" transform="translate(240)"/><use xlink:href="#111" transform="translate(260)"/><use xlink:href="#nclk" transform="translate(280)"/><use xlink:href="#000" transform="translate(300)"/><use xlink:href="#pclk" transform="translate(320)"/><use xlink:href="#111" transform="translate(340)"/><use xlink:href="#nclk" transform="translate(360)"/><use xlink:href="#000" transform="translate(380)"/><use xlink:href="#pclk" transform="translate(400)"/><use xlink:href="#111" transform="translate(420)"/></g></g><g id="wavelane_1_0" transform="translate(0,35)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>ALE0</tspan></text><g id="wavelane_draw_1_0" transform="translate(0, 0)"><use xlink:href="#xxx" transform="translate(0)"/><use xlink:href="#xxx" transform="translate(20)"/><use xlink:href="#pclk" transform="translate(40)"/><use xlink:href="#111" transform="translate(60)"/><use xlink:href="#111" transform="translate(80)"/><use xlink:href="#111" transform="translate(100)"/><use xlink:href="#nclk" transform="translate(120)"/><use xlink:href="#000" transform="translate(140)"/><use xlink:href="#000" transform="translate(160)"/><use xlink:href="#000" transform="translate(180)"/><use xlink:href="#000" transform="translate(200)"/><use xlink:href="#000" transform="translate(220)"/><use xlink:href="#000" transform="translate(240)"/><use xlink:href="#000" transform="translate(260)"/><use xlink:href="#000" transform="translate(280)"/><use xlink:href="#000" transform="translate(300)"/><use xlink:href="#000" transform="translate(320)"/><use xlink:href="#000" transform="translate(340)"/><use xlink:href="#000" transform="translate(360)"/><use xlink:href="#000" transform="translate(380)"/><use xlink:href="#0mx" transform="translate(400)"/><use xlink:href="#xxx" transform="translate(420)"/></g></g><g id="wavelane_2_0" transform="translate(0,65)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>ALE1</tspan></text><g id="wavelane_draw_2_0" transform="translate(0, 0)"><use xlink:href="#xxx" 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class="s14"/><path d="M3,0 0,0 0,20 3,20 6,10 z" class="s12"/><path d="m0,0 3,0 6,20 11,0" class="s1"/><path d="M0,20 3,20 9,0 20,0" class="s1"/></g><g id="vmv-8-9"><path d="M9,0 20,0 20,20 9,20 6,10 z" class="s14"/><path d="M3,0 0,0 0,20 3,20 6,10 z" class="s13"/><path d="m0,0 3,0 6,20 11,0" class="s1"/><path d="M0,20 3,20 9,0 20,0" class="s1"/></g><g id="vmv-9-9"><path d="M9,0 20,0 20,20 9,20 6,10 z" class="s14"/><path d="M3,0 0,0 0,20 3,20 6,10 z" class="s14"/><path d="m0,0 3,0 6,20 11,0" class="s1"/><path d="M0,20 3,20 9,0 20,0" class="s1"/></g><g id="arrow0"><path d="m-12,-3 9,3 -9,3 c 1,-2 1,-4 0,-6 z" class="s15"/><path d="M0,0 -15,0" class="s16"/></g><marker id="arrowhead" style="fill:#0041c4" markerHeight="7" markerWidth="10" markerUnits="strokeWidth" viewBox="0 -4 11 8" refX="15" refY="0" orient="auto"><path d="M0 -4 11 0 0 4z"/></marker><marker id="arrowtail" style="fill:#0041c4" markerHeight="7" markerWidth="10" markerUnits="strokeWidth" viewBox="-11 -4 11 8" refX="-15" refY="0" orient="auto"><path d="M0 -4 -11 0 0 4z"/></marker></defs><g id="waves_0"><g id="lanes_0" transform="translate(80.5, 46.5)"><g id="gmarks_0"><g style="stroke:#888;stroke-width:0.5;stroke-dasharray:1,3"><line id="gmark_0_0" x1="0" y1="0" x2="0" y2="210"/><line id="gmark_1_0" x1="40" y1="0" x2="40" y2="210"/><line id="gmark_2_0" x1="80" y1="0" x2="80" y2="210"/><line id="gmark_3_0" x1="120" y1="0" x2="120" y2="210"/><line id="gmark_4_0" x1="160" y1="0" x2="160" y2="210"/><line id="gmark_5_0" x1="200" y1="0" x2="200" y2="210"/><line id="gmark_6_0" x1="240" y1="0" x2="240" y2="210"/><line id="gmark_7_0" x1="280" y1="0" x2="280" y2="210"/><line id="gmark_8_0" x1="320" y1="0" x2="320" y2="210"/><line id="gmark_9_0" x1="360" y1="0" x2="360" y2="210"/><line id="gmark_10_0" x1="400" y1="0" x2="400" y2="210"/><line id="gmark_11_0" x1="440" y1="0" x2="440" y2="210"/></g><text x="220" y="-13" fill="#000" text-anchor="middle" xml:space="preserve"><tspan>Figure 2. Write Cycle Timing Waveform</tspan></text></g><g id="wavelane_0_0" transform="translate(0,5)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>CLK</tspan></text><g id="wavelane_draw_0_0" transform="translate(0, 0)"><use xlink:href="#111" transform="translate(0)"/><use xlink:href="#111" transform="translate(20)"/><use xlink:href="#nclk" transform="translate(40)"/><use xlink:href="#000" transform="translate(60)"/><use xlink:href="#pclk" transform="translate(80)"/><use xlink:href="#111" transform="translate(100)"/><use xlink:href="#nclk" transform="translate(120)"/><use xlink:href="#000" transform="translate(140)"/><use xlink:href="#pclk" transform="translate(160)"/><use xlink:href="#111" transform="translate(180)"/><use xlink:href="#nclk" transform="translate(200)"/><use xlink:href="#000" transform="translate(220)"/><use xlink:href="#pclk" transform="translate(240)"/><use xlink:href="#111" transform="translate(260)"/><use xlink:href="#nclk" transform="translate(280)"/><use xlink:href="#000" transform="translate(300)"/><use xlink:href="#pclk" transform="translate(320)"/><use xlink:href="#111" transform="translate(340)"/><use xlink:href="#nclk" transform="translate(360)"/><use xlink:href="#000" transform="translate(380)"/><use xlink:href="#pclk" transform="translate(400)"/><use xlink:href="#111" transform="translate(420)"/></g></g><g id="wavelane_1_0" transform="translate(0,35)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>ALE0</tspan></text><g id="wavelane_draw_1_0" transform="translate(0, 0)"><use xlink:href="#xxx" transform="translate(0)"/><use xlink:href="#xxx" transform="translate(20)"/><use xlink:href="#pclk" transform="translate(40)"/><use xlink:href="#111" transform="translate(60)"/><use xlink:href="#111" transform="translate(80)"/><use xlink:href="#111" transform="translate(100)"/><use xlink:href="#nclk" transform="translate(120)"/><use xlink:href="#000" transform="translate(140)"/><use xlink:href="#000" transform="translate(160)"/><use xlink:href="#000" transform="translate(180)"/><use xlink:href="#000" transform="translate(200)"/><use xlink:href="#000" transform="translate(220)"/><use xlink:href="#000" transform="translate(240)"/><use xlink:href="#000" transform="translate(260)"/><use xlink:href="#000" transform="translate(280)"/><use xlink:href="#000" transform="translate(300)"/><use xlink:href="#000" transform="translate(320)"/><use xlink:href="#000" transform="translate(340)"/><use xlink:href="#000" transform="translate(360)"/><use xlink:href="#000" transform="translate(380)"/><use xlink:href="#0mx" transform="translate(400)"/><use xlink:href="#xxx" transform="translate(420)"/></g></g><g id="wavelane_2_0" transform="translate(0,65)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>ALE1</tspan></text><g id="wavelane_draw_2_0" transform="translate(0, 0)"><use xlink:href="#xxx" transform="translate(0)"/><use xlink:href="#xxx" transform="translate(20)"/><use xlink:href="#nclk" transform="translate(40)"/><use xlink:href="#000" transform="translate(60)"/><use xlink:href="#000" transform="translate(80)"/><use xlink:href="#000" transform="translate(100)"/><use xlink:href="#pclk" transform="translate(120)"/><use xlink:href="#111" transform="translate(140)"/><use xlink:href="#111" transform="translate(160)"/><use xlink:href="#111" transform="translate(180)"/><use xlink:href="#nclk" transform="translate(200)"/><use xlink:href="#000" transform="translate(220)"/><use xlink:href="#000" transform="translate(240)"/><use xlink:href="#000" transform="translate(260)"/><use xlink:href="#000" transform="translate(280)"/><use xlink:href="#000" transform="translate(300)"/><use xlink:href="#000" transform="translate(320)"/><use xlink:href="#000" transform="translate(340)"/><use xlink:href="#000" transform="translate(360)"/><use xlink:href="#000" transform="translate(380)"/><use xlink:href="#000" transform="translate(400)"/><use xlink:href="#000" transform="translate(420)"/></g></g><g id="wavelane_3_0" transform="translate(0,95)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>WE#</tspan></text><g id="wavelane_draw_3_0" transform="translate(0, 0)"><use xlink:href="#111" transform="translate(0)"/><use xlink:href="#111" transform="translate(20)"/><use xlink:href="#111" transform="translate(40)"/><use xlink:href="#111" transform="translate(60)"/><use xlink:href="#111" transform="translate(80)"/><use xlink:href="#111" transform="translate(100)"/><use xlink:href="#111" transform="translate(120)"/><use xlink:href="#111" transform="translate(140)"/><use xlink:href="#111" transform="translate(160)"/><use xlink:href="#111" transform="translate(180)"/><use xlink:href="#111" transform="translate(200)"/><use xlink:href="#111" transform="translate(220)"/><use xlink:href="#nclk" transform="translate(240)"/><use xlink:href="#000" transform="translate(260)"/><use xlink:href="#000" transform="translate(280)"/><use xlink:href="#000" transform="translate(300)"/><use xlink:href="#pclk" transform="translate(320)"/><use xlink:href="#111" transform="translate(340)"/><use xlink:href="#111" transform="translate(360)"/><use xlink:href="#111" transform="translate(380)"/><use xlink:href="#111" transform="translate(400)"/><use xlink:href="#111" transform="translate(420)"/></g></g><g id="wavelane_4_0" transform="translate(0,125)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>OE#</tspan></text><g id="wavelane_draw_4_0" transform="translate(0, 0)"><use xlink:href="#111" transform="translate(0)"/><use xlink:href="#111" transform="translate(20)"/><use xlink:href="#111" transform="translate(40)"/><use xlink:href="#111" transform="translate(60)"/><use xlink:href="#111" transform="translate(80)"/><use xlink:href="#111" transform="translate(100)"/><use xlink:href="#111" transform="translate(120)"/><use xlink:href="#111" transform="translate(140)"/><use xlink:href="#111" transform="translate(160)"/><use xlink:href="#111" transform="translate(180)"/><use xlink:href="#111" transform="translate(200)"/><use xlink:href="#111" transform="translate(220)"/><use xlink:href="#nclk" transform="translate(240)"/><use xlink:href="#000" transform="translate(260)"/><use xlink:href="#000" transform="translate(280)"/><use xlink:href="#000" transform="translate(300)"/><use xlink:href="#000" transform="translate(320)"/><use xlink:href="#000" transform="translate(340)"/><use xlink:href="#pclk" transform="translate(360)"/><use xlink:href="#111" transform="translate(380)"/><use xlink:href="#111" transform="translate(400)"/><use xlink:href="#111" transform="translate(420)"/></g></g><g id="wavelane_5_0" transform="translate(0,155)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>BHE#</tspan></text><g id="wavelane_draw_5_0" transform="translate(0, 0)"><use xlink:href="#xxx" transform="translate(0)"/><use xlink:href="#xxx" transform="translate(20)"/><use xlink:href="#xxx" transform="translate(40)"/><use xlink:href="#xxx" transform="translate(60)"/><use xlink:href="#pclk" transform="translate(80)"/><use xlink:href="#111" transform="translate(100)"/><use xlink:href="#111" transform="translate(120)"/><use xlink:href="#111" transform="translate(140)"/><use xlink:href="#111" transform="translate(160)"/><use xlink:href="#111" transform="translate(180)"/><use xlink:href="#111" transform="translate(200)"/><use xlink:href="#111" transform="translate(220)"/><use xlink:href="#111" transform="translate(240)"/><use xlink:href="#111" transform="translate(260)"/><use xlink:href="#111" transform="translate(280)"/><use xlink:href="#111" transform="translate(300)"/><use xlink:href="#111" transform="translate(320)"/><use xlink:href="#111" transform="translate(340)"/><use xlink:href="#111" transform="translate(360)"/><use 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Port Mapped I/O Read Timing Waveform</tspan></text></g><g id="wavelane_0_0" transform="translate(0,5)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>CLK</tspan></text><g id="wavelane_draw_0_0" transform="translate(0, 0)"><use xlink:href="#111" transform="translate(0)"/><use xlink:href="#111" transform="translate(20)"/><use xlink:href="#nclk" transform="translate(40)"/><use xlink:href="#000" transform="translate(60)"/><use xlink:href="#pclk" transform="translate(80)"/><use xlink:href="#111" transform="translate(100)"/><use xlink:href="#nclk" transform="translate(120)"/><use xlink:href="#000" transform="translate(140)"/><use xlink:href="#pclk" transform="translate(160)"/><use xlink:href="#111" transform="translate(180)"/><use xlink:href="#nclk" transform="translate(200)"/><use xlink:href="#000" transform="translate(220)"/><use xlink:href="#pclk" transform="translate(240)"/><use xlink:href="#111" transform="translate(260)"/><use xlink:href="#nclk" transform="translate(280)"/><use xlink:href="#000" transform="translate(300)"/><use xlink:href="#pclk" transform="translate(320)"/><use xlink:href="#111" transform="translate(340)"/></g></g><g id="wavelane_1_0" transform="translate(0,35)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>ALE0</tspan></text><g id="wavelane_draw_1_0" transform="translate(0, 0)"><use xlink:href="#xxx" transform="translate(0)"/><use xlink:href="#xxx" transform="translate(20)"/><use xlink:href="#pclk" transform="translate(40)"/><use xlink:href="#111" transform="translate(60)"/><use xlink:href="#111" transform="translate(80)"/><use xlink:href="#111" transform="translate(100)"/><use xlink:href="#nclk" transform="translate(120)"/><use xlink:href="#000" transform="translate(140)"/><use xlink:href="#000" transform="translate(160)"/><use xlink:href="#000" transform="translate(180)"/><use xlink:href="#000" transform="translate(200)"/><use xlink:href="#000" transform="translate(220)"/><use xlink:href="#000" transform="translate(240)"/><use xlink:href="#000" transform="translate(260)"/><use xlink:href="#000" transform="translate(280)"/><use xlink:href="#000" transform="translate(300)"/><use xlink:href="#0mx" transform="translate(320)"/><use xlink:href="#xxx" transform="translate(340)"/></g></g><g id="wavelane_2_0" transform="translate(0,65)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>WE#</tspan></text><g id="wavelane_draw_2_0" transform="translate(0, 0)"><use xlink:href="#111" transform="translate(0)"/><use xlink:href="#111" transform="translate(20)"/><use xlink:href="#111" transform="translate(40)"/><use xlink:href="#111" transform="translate(60)"/><use xlink:href="#111" transform="translate(80)"/><use xlink:href="#111" transform="translate(100)"/><use xlink:href="#111" transform="translate(120)"/><use xlink:href="#111" transform="translate(140)"/><use xlink:href="#nclk" transform="translate(160)"/><use xlink:href="#000" transform="translate(180)"/><use xlink:href="#000" transform="translate(200)"/><use xlink:href="#000" transform="translate(220)"/><use xlink:href="#pclk" transform="translate(240)"/><use xlink:href="#111" transform="translate(260)"/><use xlink:href="#111" transform="translate(280)"/><use xlink:href="#111" transform="translate(300)"/><use xlink:href="#111" transform="translate(320)"/><use xlink:href="#111" transform="translate(340)"/></g></g><g id="wavelane_3_0" transform="translate(0,95)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>OE#</tspan></text><g id="wavelane_draw_3_0" transform="translate(0, 0)"><use xlink:href="#111" transform="translate(0)"/><use xlink:href="#111" transform="translate(20)"/><use xlink:href="#111" transform="translate(40)"/><use xlink:href="#111" transform="translate(60)"/><use xlink:href="#111" transform="translate(80)"/><use xlink:href="#111" transform="translate(100)"/><use xlink:href="#111" transform="translate(120)"/><use xlink:href="#111" transform="translate(140)"/><use xlink:href="#nclk" transform="translate(160)"/><use xlink:href="#000" transform="translate(180)"/><use xlink:href="#000" transform="translate(200)"/><use xlink:href="#000" transform="translate(220)"/><use xlink:href="#000" transform="translate(240)"/><use xlink:href="#000" transform="translate(260)"/><use xlink:href="#pclk" transform="translate(280)"/><use xlink:href="#111" transform="translate(300)"/><use xlink:href="#111" transform="translate(320)"/><use xlink:href="#111" transform="translate(340)"/></g></g><g id="wavelane_4_0" transform="translate(0,125)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>BHE#</tspan></text><g id="wavelane_draw_4_0" transform="translate(0, 0)"><use xlink:href="#xxx" transform="translate(0)"/><use xlink:href="#xxx" transform="translate(20)"/><use xlink:href="#xxx" transform="translate(40)"/><use xlink:href="#xxx" transform="translate(60)"/><use xlink:href="#pclk" transform="translate(80)"/><use xlink:href="#111" transform="translate(100)"/><use xlink:href="#111" transform="translate(120)"/><use xlink:href="#111" transform="translate(140)"/><use xlink:href="#111" transform="translate(160)"/><use xlink:href="#111" transform="translate(180)"/><use xlink:href="#111" transform="translate(200)"/><use xlink:href="#111" transform="translate(220)"/><use xlink:href="#111" transform="translate(240)"/><use xlink:href="#111" transform="translate(260)"/><use xlink:href="#111" transform="translate(280)"/><use xlink:href="#111" transform="translate(300)"/><use xlink:href="#1mx" transform="translate(320)"/><use xlink:href="#xxx" transform="translate(340)"/></g></g><g id="wavelane_5_0" transform="translate(0,155)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>IO[15:0]</tspan></text><g id="wavelane_draw_5_0" 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transform="translate(0,35)"/><g id="wavegap_2_0" transform="translate(0,65)"/><g id="wavegap_3_0" transform="translate(0,95)"/><g id="wavegap_4_0" transform="translate(0,125)"/><g id="wavegap_5_0" transform="translate(0,155)"/></g></g><g id="groups_0"><g/></g></g></svg> \ No newline at end of file
diff --git a/openlane/hs32_core1/config.tcl b/openlane/hs32_core1/config.tcl new file mode 100644 index 0000000..59ecf7c --- /dev/null +++ b/openlane/hs32_core1/config.tcl
@@ -0,0 +1,33 @@ +set script_dir [file dirname [file normalize [info script]]] + +set ::env(ROUTING_CORES) 4 + +set ::env(PDK) sky130A +set ::env(STD_CELL_LIBRARY) sky130_fd_sc_hd + +set ::env(DESIGN_NAME) hs32_core1 + +set ::env(DESIGN_IS_CORE) 0 +set ::env(GLB_RT_MAXLAYER) 5 + +set ::env(SYNTH_STRATEGY) 1 +set ::env(DIODE_INSERTION_STRATEGY) 1 + +set ::env(VERILOG_FILES) "\ + $script_dir/../../verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/hs32_user_proj/hs32_core1.v \ + $script_dir/../../verilog/rtl/hs32_user_proj/hs32_bram_ctl.v \ + $script_dir/../../verilog/rtl/hs32cpu/cpu/hs32_cpu.v \ + $script_dir/../../verilog/rtl/hs32cpu/frontend/mmio.v" + +set ::env(VERILOG_INCLUDE_DIRS) "\ + $script_dir/../../verilog/rtl/hs32cpu/" + +set ::env(CLOCK_PORT) "wb_clk_i" +set ::env(CLOCK_PERIOD) "30" + +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg +set ::env(FP_SIZING) absolute +set ::env(FP_PDN_CORE_RING) 0 +set ::env(DIE_AREA) "0 0 1010 850" +set ::env(PL_TARGET_DENSITY) 0.35
diff --git a/openlane/hs32_core1/pin_order.cfg b/openlane/hs32_core1/pin_order.cfg new file mode 100644 index 0000000..4c124bd --- /dev/null +++ b/openlane/hs32_core1/pin_order.cfg
@@ -0,0 +1,20 @@ +#BUS_SORT + +#S +wb_.* +wbs_.* +la_.* + +#N +cpu_wen_n +cpu_addr_n +cpu_dtw_n +cpu_mask_n +cpu_dtr_n + +#E +cpu_wen_e +cpu_addr_e +cpu_dtw_e +cpu_mask_e +cpu_dtr_e
diff --git a/openlane/hs32_sram/config.tcl b/openlane/hs32_sram/config.tcl new file mode 100644 index 0000000..5605a3a --- /dev/null +++ b/openlane/hs32_sram/config.tcl
@@ -0,0 +1,46 @@ +set script_dir [file dirname [file normalize [info script]]] + +set ::env(DESIGN_NAME) hs32_sram + +set ::env(CLOCK_PORT) "clk" +set ::env(CLOCK_PERIOD) "10" + +set ::env(DESIGN_IS_CORE) 0 + +set ::env(PDN_CFG) $script_dir/pdn.tcl + +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 1100 1100" + +set ::env(FP_HORIZONTAL_HALO) 5 +set ::env(FP_VERTICAL_HALO) 14 +#set ::env(FP_PDN_VOFFSET) 5 +#set ::env(FP_PDN_VPITCH) 20 +#set ::env(FP_PDN_HPITCH) 50 + +#set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg + +set ::env(PL_TARGET_DENSITY) 0.5 + +set ::env(GLB_RT_MINLAYER) 2 +set ::env(GLB_RT_MAXLAYER) 5 +set ::env(GLB_RT_ALLOW_CONGESTION) 1 + +set ::env(DIODE_INSERTION_STRATEGY) 1 + +# Disable DRC +set ::env(MAGIC_DRC_USE_GDS) 0 + +set ::env(VERILOG_FILES) "\ + $script_dir/../../verilog/rtl/defines.v\ + $script_dir/../../verilog/rtl/hs32_user_proj/hs32_sram.v" + +set ::env(VERILOG_FILES_BLACKBOX) "\ + $script_dir/../../verilog/rtl/sram_1rw1r_32_256_8_sky130.v" + +set ::env(EXTRA_LEFS) "\ + $script_dir/../../lef/sram_1rw1r_32_256_8_sky130_lp1.lef" + +set ::env(EXTRA_GDS_FILES) "\ + $script_dir/../../gds/sram_1rw1r_32_256_8_sky130_lp1.gds"
diff --git a/openlane/hs32_sram/macro_placement.cfg b/openlane/hs32_sram/macro_placement.cfg new file mode 100644 index 0000000..6aecdc7 --- /dev/null +++ b/openlane/hs32_sram/macro_placement.cfg
@@ -0,0 +1,2 @@ +SRAM_0 30 11.805 N +SRAM_1 30 482.040 N
diff --git a/openlane/hs32_sram/pdn.tcl b/openlane/hs32_sram/pdn.tcl new file mode 100644 index 0000000..cac8c69 --- /dev/null +++ b/openlane/hs32_sram/pdn.tcl
@@ -0,0 +1,34 @@ +# Power nets +set ::power_nets $::env(VDD_PIN) +set ::ground_nets $::env(GND_PIN) + +set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5" + +pdngen::specify_grid stdcell { + name grid + rails { + met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0} + } + straps { + met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} + met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)} + } + connect {{met1 met4} {met4 met5}} +} + +pdngen::specify_grid macro { + power_pins "VPWR VDD vdd" + ground_pins "VGND VSS gnd" + blockages "li1 met1 met2 met3 met4" + straps { + } + connect {{met4_PIN_ver met5}} +} + +set ::halo $::env(FP_HORIZONTAL_HALO) + +# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area +set ::rails_start_with "POWER" ; + +# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area +set ::stripes_start_with "POWER" ;
diff --git a/openlane/hs32_sram/pin_order.cfg b/openlane/hs32_sram/pin_order.cfg new file mode 100644 index 0000000..62c7fc7 --- /dev/null +++ b/openlane/hs32_sram/pin_order.cfg
@@ -0,0 +1,3 @@ +#W +cpu_.* +clk
diff --git a/verilog/rtl/hs32_user_proj/hs32_bram_ctl.v b/verilog/rtl/hs32_user_proj/hs32_bram_ctl.v new file mode 100644 index 0000000..22d7c27 --- /dev/null +++ b/verilog/rtl/hs32_user_proj/hs32_bram_ctl.v
@@ -0,0 +1,129 @@ +/** + * Copyright (c) 2020 The HSC Core Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file bram_ctl.v + * @author Kevin Dai <kevindai02@outlook.com> + * @date Created on October 26 2020, 7:12 PM + */ + +module hs32_bram_ctl ( + input wire i_clk, + input wire i_reset, + input wire[addr_width-1:0] i_addr, + output wire[31:0] o_dread, + input wire[31:0] i_dwrite, + input wire i_rw, + input wire i_stb, + output reg o_ack, + + // Terrible things + output wire [15:0] cpu_addr_n, + output wire [15:0] cpu_addr_e, + output wire [7:0] cpu_mask_n, + output wire [7:0] cpu_mask_e, + output wire [1:0] cpu_wen_n, + output wire [1:0] cpu_wen_e, + output wire [31:0] wbuf, + input wire [31:0] dbuf +); + parameter addr_width = 12; + parameter data0 = "bram0.hex"; + parameter data1 = "bram1.hex"; + parameter data2 = "bram2.hex"; + parameter data3 = "bram3.hex"; + + // 4 addresses for each bram + // Selects between current dword and next dword + wire [addr_width-3:0] a0, a1, a2, a3; + assign a0 = (addr[1:0] == 2'b00) ? + addr[addr_width-1:2] : addr[addr_width-1:2] + 1; + assign a1 = (addr[1:0] == 2'b00) || (addr[1:0] == 2'b01) ? + addr[addr_width-1:2] : addr[addr_width-1:2] + 1; + assign a2 = (addr[1:0] == 2'b11) ? + addr[addr_width-1:2] + 1 : addr[addr_width-1:2]; + assign a3 = addr[addr_width-1:2]; + // + // The read buffer shifted over. + // Regarding the ending 2 bits of the address: + // x = read, . = ignore + // a' a'+1 -> where a' = addr[addr_width-1:2] + // 00 [xxxx][....] + // 01 [.xxx][x...] + // 10 [..xx][xx..] + // 11 [...x][xxx.] + // 0123 0123 -> bram# the byte came from + // dbuf will always be in the form of [0123] + // So, an address ending in 11 should be [3012] + // + wire[31:0] dout; + assign dout = + (addr[1:0] == 2'b00) ? { dbuf[31:0] } : + (addr[1:0] == 2'b01) ? { dbuf[23:0], dbuf[31:24] } : + (addr[1:0] == 2'b10) ? { dbuf[15:0], dbuf[31:16] } : + { dbuf[ 7:0], dbuf[31:8] } ; + assign wbuf = + (addr[1:0] == 2'b00) ? { dwrite[31:0] } : + (addr[1:0] == 2'b01) ? { dwrite[ 7:0], dwrite[31:8 ] } : + (addr[1:0] == 2'b10) ? { dwrite[15:0], dwrite[31:16] } : + { dwrite[23:0], dwrite[31:24] } ; + + // Latch inputs + wire[addr_width-1:0] addr; + wire[31:0] dwrite; + assign addr = i_addr; + assign dwrite = i_dwrite; + + reg r_bsy; + assign o_dread = dout; + always @(posedge i_clk) + if(i_reset) begin + o_ack <= 0; + r_bsy <= 0; + //we <= 0; + end else begin + if(i_stb/* && !r_bsy*/) begin + o_ack <= 1; + r_bsy <= 1; + //dwrite <= i_dwrite; + //addr <= i_addr; + //we <= i_rw; + end else/* if(r_bsy)*/ begin + o_ack <= 0; + r_bsy <= 0; + end + end + + // SRAM signal generation :( + + assign cpu_mask_n[7:4] = + a0[1:0] == 2'b00 ? 4'b0001 : + a0[1:0] == 2'b01 ? 4'b0010 : + a0[1:0] == 2'b11 ? 4'b1000 : 4'b0100; + assign cpu_mask_n[3:0] = + a1[1:0] == 2'b00 ? 4'b0001 : + a1[1:0] == 2'b01 ? 4'b0010 : + a1[1:0] == 2'b11 ? 4'b1000 : 4'b0100; + assign cpu_mask_e[7:4] = + a2[1:0] == 2'b00 ? 4'b0001 : + a2[1:0] == 2'b01 ? 4'b0010 : + a2[1:0] == 2'b11 ? 4'b1000 : 4'b0100; + assign cpu_mask_e[3:0] = + a3[1:0] == 2'b00 ? 4'b0001 : + a3[1:0] == 2'b01 ? 4'b0010 : + a3[1:0] == 2'b11 ? 4'b1000 : 4'b0100; + assign { cpu_wen_n, cpu_wen_e } = { 4{!i_rw} }; + assign cpu_addr_n = { a0[9:2], a1[9:2] }; + assign cpu_addr_n = { a0[9:2], a1[9:2] }; +endmodule \ No newline at end of file
diff --git a/verilog/rtl/hs32_user_proj/hs32_user_core2.v b/verilog/rtl/hs32_user_proj/hs32_core0.v similarity index 99% rename from verilog/rtl/hs32_user_proj/hs32_user_core2.v rename to verilog/rtl/hs32_user_proj/hs32_core0.v index 07a2061..b8b73fd 100644 --- a/verilog/rtl/hs32_user_proj/hs32_user_core2.v +++ b/verilog/rtl/hs32_user_proj/hs32_core0.v
@@ -1,126 +1,126 @@ -`ifdef verilator - `include "defines.v" - `include "cpu/hs32_cpu.v" - `include "frontend/sram.v" - `include "frontend/mmio.v" -`endif - -`default_nettype none - -module hs32_user_proj ( -`ifdef USE_POWER_PINS - inout vdda1, // User area 1 3.3V supply - inout vdda2, // User area 2 3.3V supply - inout vssa1, // User area 1 analog ground - inout vssa2, // User area 2 analog ground - inout vccd1, // User area 1 1.8V supply - inout vccd2, // User area 2 1.8v supply - inout vssd1, // User area 1 digital ground - inout vssd2, // User area 2 digital ground -`endif - - // Wishbone Slave ports (WB MI A) - input wire wb_clk_i, - input wire wb_rst_i, - input wire wbs_stb_i, - input wire wbs_cyc_i, - input wire wbs_we_i, - input wire [3:0] wbs_sel_i, - input wire [31:0] wbs_dat_i, - input wire [31:0] wbs_adr_i, - output wire wbs_ack_o, - output wire [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input wire [127:0] la_data_in, - output wire [127:0] la_data_out, - input wire [127:0] la_oen, - - // IOs - input wire [`MPRJ_IO_PADS-1:0] io_in, - output wire [`MPRJ_IO_PADS-1:0] io_out, - output wire [`MPRJ_IO_PADS-1:0] io_oeb -); - // Clock and reset - // wire clk = (~la_oen[64])? la_data_in[64] : wb_clk_i; - // wire rst = (~la_oen[65])? la_data_in[65] : wb_rst_i; - wire clk = wb_clk_i; - wire rst = wb_rst_i; - - // Wishbone logic - wire valid; - wire [3:0] wstrb; - assign valid = wbs_cyc_i && wbs_stb_i; - assign wstrb = wbs_sel_i & { 4 { wbs_we_i } }; - // TODO - - // CPU Core 0 Connection - wire[31:0] adr0, dtr0, dtw0, isr0; - wire rw0, val0, rdy0, iack0, irq0, nmi0, usr0, fault0; - wire[23:0] int0; - wire[4:0] vec0; - hs32_cpu #( - .IMUL(1), .BARREL_SHIFTER(1), .PREFETCH_SIZE(3) - ) core0 ( - .i_clk(clk), .reset(rst), - // Mem - .addr(adr0), .rw(rw0), .din(dtr0), .dout(dtw0), - .valid(val0), .ready(rdy0), - // Int - .interrupts(int0), .iack(iack0), .handler(isr0), - .intrq(irq0), .vec(vec0), .nmi(nmi0), - // Misc - .userbit(usr0), .fault(fault0) - ); - - // MMIO - mmio mmio_unit( - .clk(clk), .reset(rst), - // CPU - .valid(val0), .ready(rdy0), - .addr(adr0), .dtw(dtw0), .dtr(dtr0), .rw(rw0), - // SRAM - .sval(svalid), .srdy(sready), - .saddr(saddr), .sdtw(sdtw), .sdtr(sdtr), .srw(srw), - // Interrupt controller - .interrupts(int0), .handler(isr0), .intrq(irq0), - .vec(vec0), .nmi(nmi0) - ); - - // SRAM Controller - wire sready, svalid, srw; - wire [31:0] saddr, sdtw, sdtr; - // Output - wire[15:0] data_in; - wire[15:0] data_out; - wire we, oe, oe_neg, ale0_neg, ale1_neg, bhe, isout; - ext_sram #( - .SRAM_LATCH_LAZY(1) - ) sram ( - .clk(clk), .reset(rst), - // Memory requests - .ready(sready), .valid(svalid), .rw(srw), - .addri(saddr), .dtw(sdtw), .dtr(sdtr), - // External IO interface, active >> HIGH << - .din(data_in), .dout(data_out), - .we(we), .oe(oe), .oe_negedge(oe_neg), - .ale0_negedge(ale0_neg), - .ale1_negedge(ale1_neg), - .bhe(bhe), .isout(isout) - ); - - // SRAM GPIO Logic - assign io_out[36] = usr0; - assign data_in = io_in[35:20]; - assign io_out[35:20] = data_out; - assign io_out[19] = !(oe & oe_neg); - assign io_out[18] = !we; - assign io_out[17] = ale0_neg; - assign io_out[16] = ale1_neg; - assign io_out[15] = !bhe; - - // Output enables - assign io_oeb[36] = 0; - assign io_oeb[35:20] = { (16){ ~isout } }; - assign io_oeb[19:15] = 0; +`ifdef verilator + `include "defines.v" + `include "cpu/hs32_cpu.v" + `include "frontend/sram.v" + `include "frontend/mmio.v" +`endif + +`default_nettype none + +module hs32_user_proj ( +`ifdef USE_POWER_PINS + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground +`endif + + // Wishbone Slave ports (WB MI A) + input wire wb_clk_i, + input wire wb_rst_i, + input wire wbs_stb_i, + input wire wbs_cyc_i, + input wire wbs_we_i, + input wire [3:0] wbs_sel_i, + input wire [31:0] wbs_dat_i, + input wire [31:0] wbs_adr_i, + output wire wbs_ack_o, + output wire [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input wire [127:0] la_data_in, + output wire [127:0] la_data_out, + input wire [127:0] la_oen, + + // IOs + input wire [`MPRJ_IO_PADS-1:0] io_in, + output wire [`MPRJ_IO_PADS-1:0] io_out, + output wire [`MPRJ_IO_PADS-1:0] io_oeb +); + // Clock and reset + // wire clk = (~la_oen[64])? la_data_in[64] : wb_clk_i; + // wire rst = (~la_oen[65])? la_data_in[65] : wb_rst_i; + wire clk = wb_clk_i; + wire rst = wb_rst_i; + + // Wishbone logic + wire valid; + wire [3:0] wstrb; + assign valid = wbs_cyc_i && wbs_stb_i; + assign wstrb = wbs_sel_i & { 4 { wbs_we_i } }; + // TODO + + // CPU Core 0 Connection + wire[31:0] adr0, dtr0, dtw0, isr0; + wire rw0, val0, rdy0, iack0, irq0, nmi0, usr0, fault0; + wire[23:0] int0; + wire[4:0] vec0; + hs32_cpu #( + .IMUL(1), .BARREL_SHIFTER(1), .PREFETCH_SIZE(3) + ) core0 ( + .i_clk(clk), .reset(rst), + // Mem + .addr(adr0), .rw(rw0), .din(dtr0), .dout(dtw0), + .valid(val0), .ready(rdy0), + // Int + .interrupts(int0), .iack(iack0), .handler(isr0), + .intrq(irq0), .vec(vec0), .nmi(nmi0), + // Misc + .userbit(usr0), .fault(fault0) + ); + + // MMIO + mmio mmio_unit( + .clk(clk), .reset(rst), + // CPU + .valid(val0), .ready(rdy0), + .addr(adr0), .dtw(dtw0), .dtr(dtr0), .rw(rw0), + // SRAM + .sval(svalid), .srdy(sready), + .saddr(saddr), .sdtw(sdtw), .sdtr(sdtr), .srw(srw), + // Interrupt controller + .interrupts(int0), .handler(isr0), .intrq(irq0), + .vec(vec0), .nmi(nmi0) + ); + + // SRAM Controller + wire sready, svalid, srw; + wire [31:0] saddr, sdtw, sdtr; + // Output + wire[15:0] data_in; + wire[15:0] data_out; + wire we, oe, oe_neg, ale0_neg, ale1_neg, bhe, isout; + ext_sram #( + .SRAM_LATCH_LAZY(1) + ) sram ( + .clk(clk), .reset(rst), + // Memory requests + .ready(sready), .valid(svalid), .rw(srw), + .addri(saddr), .dtw(sdtw), .dtr(sdtr), + // External IO interface, active >> HIGH << + .din(data_in), .dout(data_out), + .we(we), .oe(oe), .oe_negedge(oe_neg), + .ale0_negedge(ale0_neg), + .ale1_negedge(ale1_neg), + .bhe(bhe), .isout(isout) + ); + + // SRAM GPIO Logic + assign io_out[36] = usr0; + assign data_in = io_in[35:20]; + assign io_out[35:20] = data_out; + assign io_out[19] = !(oe & oe_neg); + assign io_out[18] = !we; + assign io_out[17] = ale0_neg; + assign io_out[16] = ale1_neg; + assign io_out[15] = !bhe; + + // Output enables + assign io_oeb[36] = 0; + assign io_oeb[35:20] = { (16){ ~isout } }; + assign io_oeb[19:15] = 0; endmodule \ No newline at end of file
diff --git a/verilog/rtl/hs32_user_proj/hs32_core1.v b/verilog/rtl/hs32_user_proj/hs32_core1.v new file mode 100644 index 0000000..eeff51c --- /dev/null +++ b/verilog/rtl/hs32_user_proj/hs32_core1.v
@@ -0,0 +1,142 @@ +`ifdef verilator + `include "defines.v" + `include "cpu/hs32_cpu.v" + `include "hs32_user_proj/hs32_bram_ctl.v" + `include "frontend/mmio.v" +`endif + +`default_nettype none + +module hs32_core1 ( +`ifdef USE_POWER_PINS + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground +`endif + + // Wishbone Slave ports (south face) + input wire wb_clk_i, + input wire wb_rst_i, + input wire wbs_stb_i, + input wire wbs_cyc_i, + input wire wbs_we_i, + input wire [3:0] wbs_sel_i, + input wire [31:0] wbs_dat_i, + input wire [31:0] wbs_adr_i, + output wire wbs_ack_o, + output wire [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input wire [127:0] la_data_in, + output wire [127:0] la_data_out, + input wire [127:0] la_oen, + + // IOs + /*input wire [`MPRJ_IO_PADS-1:0] io_in, + output wire [`MPRJ_IO_PADS-1:0] io_out, + output wire [`MPRJ_IO_PADS-1:0] io_oeb,*/ + + // Output (north and east faces) + output wire [7:0] cpu_mask_n, + output wire [7:0] cpu_mask_e, + output wire [1:0] cpu_wen_n, + output wire [1:0] cpu_wen_e, + output wire [15:0] cpu_addr_n, + output wire [15:0] cpu_addr_e, + output wire [15:0] cpu_dtw_n, + output wire [15:0] cpu_dtw_e, + input wire [15:0] cpu_dtr_n, + input wire [15:0] cpu_dtr_e +); + // Clock and reset + // wire clk = (~la_oen[64])? la_data_in[64] : wb_clk_i; + // wire rst = (~la_oen[65])? la_data_in[65] : wb_rst_i; + wire clk = wb_clk_i; + wire rst = wb_rst_i; + + // Wishbone logic + wire valid; + wire [3:0] wstrb; + assign valid = wbs_cyc_i && wbs_stb_i; + assign wstrb = wbs_sel_i & { 4 { wbs_we_i } }; + // TODO + + //===============================// + // Main CPU core + //===============================// + + wire[31:0] addr, dread, dwrite; + wire rw, stb, ack, flush; + + hs32_cpu #( + .IMUL(1), .BARREL_SHIFTER(1), .PREFETCH_SIZE(3) + ) core1 ( + .i_clk(clk), .reset(rst), + + .addr(addr), .rw(rw), + .din(dread), .dout(dwrite), + .stb(stb), .ack(ack), + + .interrupts(inte), + .iack(), .handler(isr), + .intrq(irq), .vec(ivec), + .nmi(nmi), + + .flush(flush), .fault(), .userbit() + ); + + //===============================// + // MMIO and Interrupts + //===============================// + + wire [23:0] inte; + wire [4:0] ivec; + wire [31:0] isr; + wire irq, nmi; + + mmio #( + .AICT_NUM_RE(0), .AICT_NUM_RI(0) + ) mmio_unit ( + .clk(clk), .reset(rst), + // CPU + .stb(stb), .ack(ack), + .addr(addr), .dtw(dwrite), .dtr(dread), .rw(rw), + // RAM + .sstb(ram_stb), .sack(ram_ack), .srw(ram_rw), + .saddr(ram_addr), .sdtw(ram_dwrite), .sdtr(ram_dread), + // Interrupt controller + .interrupts(inte), .handler(isr), .intrq(irq), .vec(ivec), .nmi(nmi), + // More registers + .aict_r(), .aict_w() + ); + + //===============================// + // Internal SRAM controller + //===============================// + + wire[31:0] ram_addr, ram_dread, ram_dwrite; + wire ram_rw, ram_stb, ram_ack; + + hs32_bram_ctl bram_ctl( + .i_clk(clk), + .i_reset(rst || flush), + .i_addr(ram_addr[11:0]), .i_rw(ram_rw), + .o_dread(ram_dread), .i_dwrite(ram_dwrite), + .i_stb(ram_stb), .o_ack(ram_ack), + + // Outputs + .cpu_mask_n(cpu_mask_n), + .cpu_mask_e(cpu_mask_e), + .cpu_wen_n(cpu_wen_n), + .cpu_wen_e(cpu_wen_e), + .cpu_addr_n(cpu_addr_n), + .cpu_addr_e(cpu_addr_e), + .dbuf({ cpu_dtr_n, cpu_dtr_e }), + .wbuf({ cpu_dtw_n, cpu_dtw_e }) + ); +endmodule \ No newline at end of file
diff --git a/verilog/rtl/hs32_user_proj/hs32_ram.v b/verilog/rtl/hs32_user_proj/hs32_ram.v deleted file mode 100644 index 40d444c..0000000 --- a/verilog/rtl/hs32_user_proj/hs32_ram.v +++ /dev/null
@@ -1,95 +0,0 @@ -`ifdef verilator - `include "defines.v" -`endif - -`default_nettype none - -module storage ( - input wire clk, - input wire[addr_width-1:0] addr, - output reg [31:0] dread, - input wire[31:0] dwrite, - input wire rw, - input wire valid, - output reg ready -); - parameter addr_width = 8; - - // 4 addresses for each bram - // Selects between current dword and next dword - wire [addr_width-3:0] a0, a1, a2, a3; - assign a0 = (addr[1:0] == 2'b00) ? - addr[addr_width-1:2] : addr[addr_width-1:2] + 1; - assign a1 = (addr[1:0] == 2'b00) || (addr[1:0] == 2'b01) ? - addr[addr_width-1:2] : addr[addr_width-1:2] + 1; - assign a2 = (addr[1:0] == 2'b11) ? - addr[addr_width-1:2] + 1 : addr[addr_width-1:2]; - assign a3 = addr[addr_width-1:2]; - // - // The read buffer shifted over. - // Regarding the ending 2 bits of the address: - // x = read, . = ignore - // a' a'+1 -> where a' = addr[addr_width-1:2] - // 00 [xxxx][....] - // 01 [.xxx][x...] - // 10 [..xx][xx..] - // 11 [...x][xxx.] - // 0123 0123 -> bram# the byte came from - // dbuf will always be in the form of [0123] - // So, an address ending in 11 should be [3012] - // - wire[31:0] dout; - wire[31:0] dbuf, wbuf; - assign dout = - (addr[1:0] == 2'b00) ? { dbuf[31:0] } : - (addr[1:0] == 2'b01) ? { dbuf[23:0], dbuf[31:24] } : - (addr[1:0] == 2'b10) ? { dbuf[15:0], dbuf[31:16] } : - { dbuf[ 7:0], dbuf[31:8] } ; - assign wbuf = - (addr[1:0] == 2'b00) ? { dwrite[31:0] } : - (addr[1:0] == 2'b01) ? { dwrite[ 7:0], dwrite[31:8 ] } : - (addr[1:0] == 2'b10) ? { dwrite[15:0], dwrite[31:16] } : - { dwrite[23:0], dwrite[31:24] } ; - - // Write enable signal - wire we; assign we = valid & rw; - - // FSM (needed?) - reg[1:0] state = 0; - always @(posedge clk) case(state) - 0: begin - if(valid) begin - state <= 1; - end - ready <= 1; - dread <= dout; - end - 1: begin - state <= 0; - ready <= 0; - end - endcase - - sram_1rw1r_32_256_8_sky130 SRAM_0 ( - // MGMT R/W port - .clk0(clk), - .csb0(mgmt_ena[0]), - .web0(mgmt_wen[0]), - .wmask0(mgmt_wen_mask[3:0]), - .addr0(addr), - .din0(dwrite), - .dout0(dread) - ); - - sram_1rw1r_32_256_8_sky130 SRAM_1 ( - // MGMT R/W port - .clk0(mgmt_clk), - .csb0(mgmt_ena[1]), - .web0(mgmt_wen[1]), - .wmask0(mgmt_wen_mask[7:4]), - .addr0(mgmt_addr), - .din0(mgmt_wdata), - .dout0(mgmt_rdata[63:32]) - ); -endmodule -`default_nettype wire
diff --git a/verilog/rtl/hs32_user_proj/hs32_sram.v b/verilog/rtl/hs32_user_proj/hs32_sram.v new file mode 100644 index 0000000..c66da9f --- /dev/null +++ b/verilog/rtl/hs32_user_proj/hs32_sram.v
@@ -0,0 +1,71 @@ +`default_nettype none +`ifdef verilator + `include "defines.v" + `include "sram_1rw1r_32_256_8_sky130.v" +`endif + +module hs32_sram ( + input clk, +`ifdef USE_POWER_PINS + inout vdd; + inout gnd; +`endif + input [1:0] cpu_we_n, + input [9:0] cpu_addr0, + input [9:0] cpu_addr1, + input [7:0] cpu_dtw0, + input [7:0] cpu_dtw1, + input [3:0] cpu_mask0, + input [3:0] cpu_mask1, + output [7:0] cpu_dtr0, + output [7:0] cpu_dtr1, +); + /*wire[3:0] mask0 = + cpu_addr0[1:0] == 2'b00 ? 4'b0001 : + cpu_addr0[1:0] == 2'b01 ? 4'b0010 : + cpu_addr0[1:0] == 2'b11 ? 4'b1000 : 4'b0100; + wire[3:0] mask1 = + cpu_addr1[1:0] == 2'b00 ? 4'b0001 : + cpu_addr1[1:0] == 2'b01 ? 4'b0010 : + cpu_addr1[1:0] == 2'b11 ? 4'b1000 : 4'b0100;*/ + + sram_1rw1r_32_256_8_sky130 SRAM_0 ( + .clk0(clk), + .csb0(0), + .web0(cpu_we_n[0]), + .wmask0(cpu_mask0), + .addr0(cpu_addr0[9:2]), + .din0({ cpu_dtw0, cpu_dtw0, cpu_dtw0, cpu_dtw0 }), + .dout0(cpu_dtr0), + + .clk1(), + .csb1(), + .addr1(), + .dout1() + ); + + sram_1rw1r_32_256_8_sky130 SRAM_1 ( + .clk0(clk), + .csb0(0), + .web0(cpu_we_n[1]), + .wmask0(cpu_mask1), + .addr0(cpu_addr1[9:2]), + .din0({ cpu_dtw1, cpu_dtw1, cpu_dtw1, cpu_dtw1 }), + .dout0(cpu_dtr1), + + .clk1(), + .csb1(), + .addr1(), + .dout1() + ); + + /*wire[31:0] rbuf0, rbuf1; + assign cpu_dtr0 = + cpu_addr0[1:0] == 2'b00 ? rbuf0[7:0] : + cpu_addr0[1:0] == 2'b01 ? rbuf0[15:8] : + cpu_addr0[1:0] == 2'b11 ? rbuf0[31:24] : rbuf0[23:16]; + assign cpu_dtr1 = + cpu_addr0[1:0] == 2'b00 ? rbuf1[7:0] : + cpu_addr0[1:0] == 2'b01 ? rbuf1[15:8] : + cpu_addr0[1:0] == 2'b11 ? rbuf1[31:24] : rbuf1[23:16];*/ +endmodule
diff --git a/verilog/rtl/hs32_user_proj/hs32_user_proj.v b/verilog/rtl/hs32_user_proj/hs32_user_proj.v deleted file mode 100644 index 07a2061..0000000 --- a/verilog/rtl/hs32_user_proj/hs32_user_proj.v +++ /dev/null
@@ -1,126 +0,0 @@ -`ifdef verilator - `include "defines.v" - `include "cpu/hs32_cpu.v" - `include "frontend/sram.v" - `include "frontend/mmio.v" -`endif - -`default_nettype none - -module hs32_user_proj ( -`ifdef USE_POWER_PINS - inout vdda1, // User area 1 3.3V supply - inout vdda2, // User area 2 3.3V supply - inout vssa1, // User area 1 analog ground - inout vssa2, // User area 2 analog ground - inout vccd1, // User area 1 1.8V supply - inout vccd2, // User area 2 1.8v supply - inout vssd1, // User area 1 digital ground - inout vssd2, // User area 2 digital ground -`endif - - // Wishbone Slave ports (WB MI A) - input wire wb_clk_i, - input wire wb_rst_i, - input wire wbs_stb_i, - input wire wbs_cyc_i, - input wire wbs_we_i, - input wire [3:0] wbs_sel_i, - input wire [31:0] wbs_dat_i, - input wire [31:0] wbs_adr_i, - output wire wbs_ack_o, - output wire [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input wire [127:0] la_data_in, - output wire [127:0] la_data_out, - input wire [127:0] la_oen, - - // IOs - input wire [`MPRJ_IO_PADS-1:0] io_in, - output wire [`MPRJ_IO_PADS-1:0] io_out, - output wire [`MPRJ_IO_PADS-1:0] io_oeb -); - // Clock and reset - // wire clk = (~la_oen[64])? la_data_in[64] : wb_clk_i; - // wire rst = (~la_oen[65])? la_data_in[65] : wb_rst_i; - wire clk = wb_clk_i; - wire rst = wb_rst_i; - - // Wishbone logic - wire valid; - wire [3:0] wstrb; - assign valid = wbs_cyc_i && wbs_stb_i; - assign wstrb = wbs_sel_i & { 4 { wbs_we_i } }; - // TODO - - // CPU Core 0 Connection - wire[31:0] adr0, dtr0, dtw0, isr0; - wire rw0, val0, rdy0, iack0, irq0, nmi0, usr0, fault0; - wire[23:0] int0; - wire[4:0] vec0; - hs32_cpu #( - .IMUL(1), .BARREL_SHIFTER(1), .PREFETCH_SIZE(3) - ) core0 ( - .i_clk(clk), .reset(rst), - // Mem - .addr(adr0), .rw(rw0), .din(dtr0), .dout(dtw0), - .valid(val0), .ready(rdy0), - // Int - .interrupts(int0), .iack(iack0), .handler(isr0), - .intrq(irq0), .vec(vec0), .nmi(nmi0), - // Misc - .userbit(usr0), .fault(fault0) - ); - - // MMIO - mmio mmio_unit( - .clk(clk), .reset(rst), - // CPU - .valid(val0), .ready(rdy0), - .addr(adr0), .dtw(dtw0), .dtr(dtr0), .rw(rw0), - // SRAM - .sval(svalid), .srdy(sready), - .saddr(saddr), .sdtw(sdtw), .sdtr(sdtr), .srw(srw), - // Interrupt controller - .interrupts(int0), .handler(isr0), .intrq(irq0), - .vec(vec0), .nmi(nmi0) - ); - - // SRAM Controller - wire sready, svalid, srw; - wire [31:0] saddr, sdtw, sdtr; - // Output - wire[15:0] data_in; - wire[15:0] data_out; - wire we, oe, oe_neg, ale0_neg, ale1_neg, bhe, isout; - ext_sram #( - .SRAM_LATCH_LAZY(1) - ) sram ( - .clk(clk), .reset(rst), - // Memory requests - .ready(sready), .valid(svalid), .rw(srw), - .addri(saddr), .dtw(sdtw), .dtr(sdtr), - // External IO interface, active >> HIGH << - .din(data_in), .dout(data_out), - .we(we), .oe(oe), .oe_negedge(oe_neg), - .ale0_negedge(ale0_neg), - .ale1_negedge(ale1_neg), - .bhe(bhe), .isout(isout) - ); - - // SRAM GPIO Logic - assign io_out[36] = usr0; - assign data_in = io_in[35:20]; - assign io_out[35:20] = data_out; - assign io_out[19] = !(oe & oe_neg); - assign io_out[18] = !we; - assign io_out[17] = ale0_neg; - assign io_out[16] = ale1_neg; - assign io_out[15] = !bhe; - - // Output enables - assign io_oeb[36] = 0; - assign io_oeb[35:20] = { (16){ ~isout } }; - assign io_oeb[19:15] = 0; -endmodule \ No newline at end of file
diff --git a/verilog/rtl/hs32_user_proj/hs32_wrapper.v b/verilog/rtl/hs32_user_proj/hs32_wrapper.v new file mode 100644 index 0000000..5e817d5 --- /dev/null +++ b/verilog/rtl/hs32_user_proj/hs32_wrapper.v
@@ -0,0 +1,51 @@ +`default_nettype none + +`ifdef verilator + `include "defines.v" +`endif + +module user_project_wrapper ( +`ifdef USE_POWER_PINS + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground +`endif + + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output wbs_ack_o, + output [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oen, + + // IOs + input [`MPRJ_IO_PADS-1:0] io_in, + output [`MPRJ_IO_PADS-1:0] io_out, + output [`MPRJ_IO_PADS-1:0] io_oeb, + + // Analog (direct connection to GPIO pad---use with caution) + // Note that analog I/O is not available on the 7 lowest-numbered + // GPIO pads, and so the analog_io indexing is offset from the + // GPIO indexing by 7. + inout [`MPRJ_IO_PADS-8:0] analog_io, + + // Independent clock (on independent integer divider) + input user_clock2 +); + +endmodule
diff --git a/verilog/rtl/hs32cpu b/verilog/rtl/hs32cpu index 38bed55..512eeba 160000 --- a/verilog/rtl/hs32cpu +++ b/verilog/rtl/hs32cpu
@@ -1 +1 @@ -Subproject commit 38bed554e73629094f01835bf37a27eb20404ab3 +Subproject commit 512eeba101ecedd60a5466e57a7ef15f5229cd83
