Update files part 1

Co-authored-by: Anthony Kung <hi@anth.dev>

.gitignore

diff --git a/.gitignore b/.gitignore
index 144d6b6..81384c3 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,3 +7,5 @@
 *.bin
 *.vvp
 *.idx
+*.out
+*.out1

macros/bm/sram_1rw1r_32_256_8_sky130.v

diff --git a/macros/bm/sram_1rw1r_32_256_8_sky130.v b/macros/bm/sram_1rw1r_32_256_8_sky130.v
index 84d7514..dc44912 100644
--- a/macros/bm/sram_1rw1r_32_256_8_sky130.v
+++ b/macros/bm/sram_1rw1r_32_256_8_sky130.v
@@ -57,6 +57,8 @@
 `ifdef DBG
     if ( !csb0_reg && web0_reg ) 
       $display($time," Reading %m addr0=%X dout0=%X",addr0_reg,mem[addr0_reg]);
+`endif
+`ifdef SRAM_LOG
     if ( !csb0_reg && !web0_reg )
       $display($time," Writing %m addr0=%X din0=%X wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
 `endif

openlane/hs32_core1/config.tcl

diff --git a/openlane/hs32_core1/config.tcl b/openlane/hs32_core1/config.tcl
index 2a6b69a..c137ed3 100644
--- a/openlane/hs32_core1/config.tcl
+++ b/openlane/hs32_core1/config.tcl
@@ -33,3 +33,6 @@
 set ::env(FP_PDN_CORE_RING) 0
 set ::env(DIE_AREA) "0 0 1100 1100"
 set ::env(PL_TARGET_DENSITY) 0.40
+
+set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]

openlane/hs32_core1/pin_order.cfg

diff --git a/openlane/hs32_core1/pin_order.cfg b/openlane/hs32_core1/pin_order.cfg
index 3502671..a49940f 100644
--- a/openlane/hs32_core1/pin_order.cfg
+++ b/openlane/hs32_core1/pin_order.cfg
@@ -4,6 +4,7 @@
 wb_.*
 wbs_.*
 la_.*
+io_.*
 
 #N
 cpu_mask_n.*

openlane/user_project_wrapper/interactive.tcl

diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index 9af67f1..a55efd5 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -24,15 +24,18 @@
 add_macro_placement sram4 1550 1600 S;  # RX buffer for core1
 add_macro_placement sram5 2200 1600 N;  # RX buffer for core0
 
-
 manual_macro_placement f
 
 exec -ignorestderr openroad -exit $script_dir/gen_pdn.tcl
 set_def $::env(pdn_tmp_file_tag).def
 
 global_routing_or
+add_route_obs
 detailed_routing
 
+write_powered_verilog -power vccd1 -ground vssd1
+set_netlist $::env(lvs_result_file_tag).powered.v
+
 run_magic
 run_magic_spice_export
 

openlane/user_project_wrapper/pin_order.cfg

diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
index 0717c4b..6de1406 100644
--- a/openlane/user_project_wrapper/pin_order.cfg
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -1 +1,157 @@
-../user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file
+#BUS_SORT
+#NR
+analog_io\[15\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+analog_io\[16\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+analog_io\[17\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+analog_io\[18\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+analog_io\[19\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+analog_io\[20\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+analog_io\[21\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+analog_io\[22\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+analog_io\[23\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+
+#E
+analog_io\[0\]
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+analog_io\[1\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+analog_io\[2\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+analog_io\[3\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+analog_io\[4\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+analog_io\[5\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+analog_io\[6\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+analog_io\[7\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+analog_io\[8\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+analog_io\[9\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+analog_io\[10\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+analog_io\[11\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+analog_io\[12\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+analog_io\[13\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+analog_io\[14\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+analog_io\[24\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+analog_io\[25\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+analog_io\[26\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+analog_io\[27\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+analog_io\[28\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+analog_io\[29\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+analog_io\[30\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]

verilog/dv/caravel/hs32_soc/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/Makefile b/verilog/dv/caravel/hs32_soc/Makefile
new file mode 100644
index 0000000..8352036
--- /dev/null
+++ b/verilog/dv/caravel/hs32_soc/Makefile
@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = core1test1 core1test2 core1test3 core1test4 core1test5 core1test6
+
+all:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make &> verify.log && grep Monitor verify.log) ; \
+	done
+
+clean:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make clean ) ; \
+	done
+
+.PHONY: clean all

verilog/dv/caravel/hs32_soc/core1mem/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1mem/Makefile b/verilog/dv/caravel/hs32_soc/core1mem/Makefile
index e6f909c..271ceb4 100644
--- a/verilog/dv/caravel/hs32_soc/core1mem/Makefile
+++ b/verilog/dv/caravel/hs32_soc/core1mem/Makefile
@@ -37,6 +37,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.idx
 
 .PHONY: clean hex all

verilog/dv/caravel/hs32_soc/core1mem/mem_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1mem/mem_tb.v b/verilog/dv/caravel/hs32_soc/core1mem/mem_tb.v
index ba9d7f1..04405ba 100644
--- a/verilog/dv/caravel/hs32_soc/core1mem/mem_tb.v
+++ b/verilog/dv/caravel/hs32_soc/core1mem/mem_tb.v
@@ -66,9 +66,9 @@
 
 	initial begin
 	    // Some weak test cases
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[0] == 16'hCAFE);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[1] == 16'h5);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[2] == 16'hCAFE);
+	    wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[0] == 16'hCAFE);
+	    wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[1] == 16'h5);
+	    wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[2] == 16'hCAFE);
 	    $display("Test 1 [MOV, LDR, STR Variant 1] Passed Weak Cases");
 	    //$finish;
 	end

verilog/dv/caravel/hs32_soc/core1mem/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1mem/tb.gtkw b/verilog/dv/caravel/hs32_soc/core1mem/tb.gtkw
index 361d82b..cd40e11 100644
--- a/verilog/dv/caravel/hs32_soc/core1mem/tb.gtkw
+++ b/verilog/dv/caravel/hs32_soc/core1mem/tb.gtkw
@@ -14,8 +14,8 @@
 [treeopen] tb.uut.
 [treeopen] tb.uut.mprj.
 [treeopen] tb.uut.mprj.core1.
-[treeopen] tb.uut.mprj.core1.core1.
-[treeopen] tb.uut.mprj.core1.core1.EXEC.
+[treeopen] tb.uut.mprj.core1.core.
+[treeopen] tb.uut.mprj.core1.core.EXEC.
 [treeopen] tb.uut.mprj.sram0.
 [sst_width] 265
 [signals_width] 269
@@ -51,14 +51,14 @@
 @c00200
 -PQ
 @22
-tb.uut.mprj.core1.core1.FETCH.\fifo[0][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[1][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[2][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[3][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[4][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[5][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[6][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[7][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[0][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[1][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[2][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[3][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[4][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[5][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[6][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[7][31:0]
 @1401200
 -PQ
 @800200
@@ -104,198 +104,198 @@
 @c00200
 -Decode
 @28
-tb.uut.mprj.core1.core1.DECODE.clk
-tb.uut.mprj.core1.core1.DECODE.reset
+tb.uut.mprj.core1.core.DECODE.clk
+tb.uut.mprj.core1.core.DECODE.reset
 @22
-tb.uut.mprj.core1.core1.DECODE.int_line[23:0]
+tb.uut.mprj.core1.core.DECODE.int_line[23:0]
 @28
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.reqd
+tb.uut.mprj.core1.core.DECODE.reqd
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.rdyd
+tb.uut.mprj.core1.core.DECODE.rdyd
 @200
 -
 @28
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.reqe
+tb.uut.mprj.core1.core.DECODE.reqe
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.rdye
-tb.uut.mprj.core1.core1.DECODE.full
+tb.uut.mprj.core1.core.DECODE.rdye
+tb.uut.mprj.core1.core.DECODE.full
 @200
 -
 @22
-tb.uut.mprj.core1.core1.DECODE.instd[31:0]
+tb.uut.mprj.core1.core.DECODE.instd[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.DECODE.aluop[3:0]
+tb.uut.mprj.core1.core.DECODE.aluop[3:0]
 @28
-tb.uut.mprj.core1.core1.DECODE.bank[1:0]
+tb.uut.mprj.core1.core.DECODE.bank[1:0]
 @22
-tb.uut.mprj.core1.core1.DECODE.ctlsig[15:0]
-tb.uut.mprj.core1.core1.DECODE.imm[15:0]
-tb.uut.mprj.core1.core1.DECODE.rd[3:0]
-tb.uut.mprj.core1.core1.DECODE.rm[3:0]
-tb.uut.mprj.core1.core1.DECODE.rn[3:0]
-tb.uut.mprj.core1.core1.DECODE.shift[4:0]
+tb.uut.mprj.core1.core.DECODE.ctlsig[15:0]
+tb.uut.mprj.core1.core.DECODE.imm[15:0]
+tb.uut.mprj.core1.core.DECODE.rd[3:0]
+tb.uut.mprj.core1.core.DECODE.rm[3:0]
+tb.uut.mprj.core1.core.DECODE.rn[3:0]
+tb.uut.mprj.core1.core.DECODE.shift[4:0]
 @1401200
 -Decode
 @c00200
 -Execute
 @28
-tb.uut.mprj.core1.core1.EXEC.clk
+tb.uut.mprj.core1.core.EXEC.clk
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.req
+tb.uut.mprj.core1.core.EXEC.req
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.rdy
+tb.uut.mprj.core1.core.EXEC.rdy
 @22
-tb.uut.mprj.core1.core1.EXEC.state[3:0]
+tb.uut.mprj.core1.core.EXEC.state[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.fault
-tb.uut.mprj.core1.core1.EXEC.int_inval
+tb.uut.mprj.core1.core.EXEC.fault
+tb.uut.mprj.core1.core.EXEC.int_inval
 @c00200
 -Module I/O
 @28
-tb.uut.mprj.core1.core1.EXEC.flush
+tb.uut.mprj.core1.core.EXEC.flush
 @22
-tb.uut.mprj.core1.core1.EXEC.newpc[31:0]
+tb.uut.mprj.core1.core.EXEC.newpc[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.aluop[3:0]
-tb.uut.mprj.core1.core1.EXEC.shift[4:0]
-tb.uut.mprj.core1.core1.EXEC.imm[15:0]
-tb.uut.mprj.core1.core1.EXEC.rd[3:0]
-tb.uut.mprj.core1.core1.EXEC.rm[3:0]
-tb.uut.mprj.core1.core1.EXEC.rn[3:0]
+tb.uut.mprj.core1.core.EXEC.aluop[3:0]
+tb.uut.mprj.core1.core.EXEC.shift[4:0]
+tb.uut.mprj.core1.core.EXEC.imm[15:0]
+tb.uut.mprj.core1.core.EXEC.rd[3:0]
+tb.uut.mprj.core1.core.EXEC.rm[3:0]
+tb.uut.mprj.core1.core.EXEC.rn[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.ctlsig[15:0]
-tb.uut.mprj.core1.core1.EXEC.bank[1:0]
+tb.uut.mprj.core1.core.EXEC.ctlsig[15:0]
+tb.uut.mprj.core1.core.EXEC.bank[1:0]
 @200
 -
 @28
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.stbm
+tb.uut.mprj.core1.core.EXEC.stbm
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.ackm
+tb.uut.mprj.core1.core.EXEC.ackm
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.stlm
+tb.uut.mprj.core1.core.EXEC.stlm
 @22
-tb.uut.mprj.core1.core1.EXEC.addr[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtwm[31:0]
+tb.uut.mprj.core1.core.EXEC.addr[31:0]
+tb.uut.mprj.core1.core.EXEC.dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtwm[31:0]
 @28
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.rw_mem
+tb.uut.mprj.core1.core.EXEC.rw_mem
 @200
 -
 @28
-tb.uut.mprj.core1.core1.EXEC.intrq
+tb.uut.mprj.core1.core.EXEC.intrq
 @1401200
 -Module I/O
 @c00200
 -Internal Bus
 @22
-tb.uut.mprj.core1.core1.EXEC.ibus1[31:0]
-tb.uut.mprj.core1.core1.EXEC.ibus2[31:0]
-tb.uut.mprj.core1.core1.EXEC.obus[31:0]
-tb.uut.mprj.core1.core1.EXEC.aluout[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus1[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus2[31:0]
+tb.uut.mprj.core1.core.EXEC.obus[31:0]
+tb.uut.mprj.core1.core.EXEC.aluout[31:0]
 @1401200
 -Internal Bus
 @c00200
 -ALU
 @22
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv[3:0]
+tb.uut.mprj.core1.core.EXEC.alu_nzcv[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv_out[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.carry
+tb.uut.mprj.core1.core.EXEC.alu_nzcv_out[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.carry
 @22
-tb.uut.mprj.core1.core1.EXEC.alu.i_a[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_b[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_op[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_r[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_a[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_b[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_op[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_r[31:0]
 @1401200
 -ALU
 @c00200
 -Special Registers
 @22
-tb.uut.mprj.core1.core1.EXEC.r_dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtw[31:0]
-tb.uut.mprj.core1.core1.EXEC.mar[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_u[31:0]
-tb.uut.mprj.core1.core1.EXEC.lr_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.sp_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.mcr_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.flags[31:0]
+tb.uut.mprj.core1.core.EXEC.r_dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtw[31:0]
+tb.uut.mprj.core1.core.EXEC.mar[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_s[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_u[31:0]
+tb.uut.mprj.core1.core.EXEC.lr_i[31:0]
+tb.uut.mprj.core1.core.EXEC.sp_i[31:0]
+tb.uut.mprj.core1.core.EXEC.mcr_s[31:0]
+tb.uut.mprj.core1.core.EXEC.flags[31:0]
 @1401200
 -Special Registers
 @c00200
 -Register Control
 @28
-tb.uut.mprj.core1.core1.EXEC.reg_we
-tb.uut.mprj.core1.core1.EXEC.reg_we_s
-tb.uut.mprj.core1.core1.EXEC.reg_we_u
+tb.uut.mprj.core1.core.EXEC.reg_we
+tb.uut.mprj.core1.core.EXEC.reg_we_s
+tb.uut.mprj.core1.core.EXEC.reg_we_u
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.regadra[3:0]
-tb.uut.mprj.core1.core1.EXEC.regouta[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_u[31:0]
+tb.uut.mprj.core1.core.EXEC.regadra[3:0]
+tb.uut.mprj.core1.core.EXEC.regouta[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_u[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.regadrb[3:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_u[31:0]
+tb.uut.mprj.core1.core.EXEC.regadrb[3:0]
+tb.uut.mprj.core1.core.EXEC.regoutb[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_u[31:0]
 @1401200
 -Register Control
 @c00200
 -Supervisor Regfile
 @22
-tb.uut.mprj.core1.core1.EXEC.regfile_s.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[15][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[15][31:0]
 @1401200
 -Supervisor Regfile
 @c00200
 -User Regfile
 @22
-tb.uut.mprj.core1.core1.EXEC.regfile_u.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[15][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[15][31:0]
 @1401200
 -User Regfile
 -Execute

verilog/dv/caravel/hs32_soc/core1test1.no/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test1.no/tb.gtkw b/verilog/dv/caravel/hs32_soc/core1test1.no/tb.gtkw
deleted file mode 100644
index 62050ed..0000000
--- a/verilog/dv/caravel/hs32_soc/core1test1.no/tb.gtkw
+++ /dev/null
@@ -1,285 +0,0 @@
-[*]
-[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
-[*] Wed Dec 16 20:43:24 2020
-[*]
-[dumpfile] "/data/caravel-hs32core/verilog/dv/caravel/hs32_soc/core1test1/dump.vcd"
-[dumpfile_mtime] "Wed Dec 16 20:32:20 2020"
-[dumpfile_size] 314705958
-[savefile] "/data/caravel-hs32core/verilog/dv/caravel/hs32_soc/core1test1/tb.gtkw"
-[timestart] 227850300
-[size] 1536 801
-[pos] -1 -1
-*-16.106964 227940000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-[treeopen] tb.
-[treeopen] tb.uut.
-[treeopen] tb.uut.mprj.
-[treeopen] tb.uut.mprj.core1.
-[treeopen] tb.uut.mprj.core1.core1.
-[treeopen] tb.uut.mprj.core1.core1.EXEC.
-[sst_width] 265
-[signals_width] 269
-[sst_expanded] 1
-[sst_vpaned_height] 222
-@c00200
--WBS
-@28
-tb.uut.mprj.wb_clk_i
-tb.uut.mprj.wb_rst_i
-tb.uut.mprj.wbs_ack_o
-@22
-tb.uut.mprj.wbs_adr_i[31:0]
-@28
-tb.uut.mprj.wbs_cyc_i
-@22
-tb.uut.mprj.wbs_dat_i[31:0]
-tb.uut.mprj.wbs_dat_o[31:0]
-tb.uut.mprj.wbs_sel_i[3:0]
-@28
-tb.uut.mprj.wbs_stb_i
-tb.uut.mprj.wbs_we_i
-@1401200
--WBS
-@28
-tb.uut.mprj.core1.ram_ce
-tb.uut.mprj.core1.bsy
-tb.uut.mprj.sram0.csb0
-tb.uut.mprj.sram0.csb0_reg
-@c00200
--PQ
-@22
-tb.uut.mprj.core1.core1.FETCH.\fifo[0][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[1][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[2][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[3][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[4][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[5][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[6][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[7][31:0]
-@1401200
--PQ
-@800200
--BRAM CTL
-@22
-tb.uut.mprj.core1.bram_ctl.i_addr[11:0]
-@28
-tb.uut.mprj.core1.bram_ctl.i_clk
-@22
-tb.uut.mprj.core1.bram_ctl.i_dwrite[31:0]
-@28
-tb.uut.mprj.core1.bram_ctl.i_reset
-tb.uut.mprj.core1.bram_ctl.i_rw
-[color] 3
-tb.uut.mprj.core1.bram_ctl.i_stb
-[color] 3
-tb.uut.mprj.core1.bram_ctl.o_ack
-@22
-tb.uut.mprj.core1.bram_ctl.o_dread[31:0]
-@28
-tb.uut.mprj.core1.bram_ctl.r_bsy
-@200
--
-@22
-tb.uut.mprj.core1.bram_ctl.r_dread[31:0]
-tb.uut.mprj.core1.bram_ctl.dbuf[31:0]
-@1000200
--BRAM CTL
-@c00200
--Decode
-@28
-tb.uut.mprj.core1.core1.DECODE.clk
-tb.uut.mprj.core1.core1.DECODE.reset
-@22
-tb.uut.mprj.core1.core1.DECODE.int_line[23:0]
-@28
-[color] 3
-tb.uut.mprj.core1.core1.DECODE.reqd
-[color] 3
-tb.uut.mprj.core1.core1.DECODE.rdyd
-@200
--
-@28
-[color] 3
-tb.uut.mprj.core1.core1.DECODE.reqe
-[color] 3
-tb.uut.mprj.core1.core1.DECODE.rdye
-tb.uut.mprj.core1.core1.DECODE.full
-@200
--
-@22
-tb.uut.mprj.core1.core1.DECODE.instd[31:0]
-@200
--
-@22
-tb.uut.mprj.core1.core1.DECODE.aluop[3:0]
-@28
-tb.uut.mprj.core1.core1.DECODE.bank[1:0]
-@22
-tb.uut.mprj.core1.core1.DECODE.ctlsig[15:0]
-tb.uut.mprj.core1.core1.DECODE.imm[15:0]
-tb.uut.mprj.core1.core1.DECODE.rd[3:0]
-tb.uut.mprj.core1.core1.DECODE.rm[3:0]
-tb.uut.mprj.core1.core1.DECODE.rn[3:0]
-tb.uut.mprj.core1.core1.DECODE.shift[4:0]
-@1401200
--Decode
-@c00200
--Execute
-@28
-tb.uut.mprj.core1.core1.EXEC.clk
-[color] 3
-tb.uut.mprj.core1.core1.EXEC.req
-[color] 3
-tb.uut.mprj.core1.core1.EXEC.rdy
-@22
-tb.uut.mprj.core1.core1.EXEC.state[3:0]
-@28
-tb.uut.mprj.core1.core1.EXEC.fault
-tb.uut.mprj.core1.core1.EXEC.int_inval
-@800200
--Module I/O
-@28
-tb.uut.mprj.core1.core1.EXEC.flush
-@22
-tb.uut.mprj.core1.core1.EXEC.newpc[31:0]
-@200
--
-@22
-tb.uut.mprj.core1.core1.EXEC.aluop[3:0]
-tb.uut.mprj.core1.core1.EXEC.shift[4:0]
-tb.uut.mprj.core1.core1.EXEC.imm[15:0]
-tb.uut.mprj.core1.core1.EXEC.rd[3:0]
-tb.uut.mprj.core1.core1.EXEC.rm[3:0]
-tb.uut.mprj.core1.core1.EXEC.rn[3:0]
-@28
-tb.uut.mprj.core1.core1.EXEC.ctlsig[15:0]
-tb.uut.mprj.core1.core1.EXEC.bank[1:0]
-@200
--
-@28
-[color] 3
-tb.uut.mprj.core1.core1.EXEC.stbm
-[color] 3
-tb.uut.mprj.core1.core1.EXEC.ackm
-[color] 3
-tb.uut.mprj.core1.core1.EXEC.stlm
-@22
-tb.uut.mprj.core1.core1.EXEC.addr[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtwm[31:0]
-@28
-[color] 3
-tb.uut.mprj.core1.core1.EXEC.rw_mem
-@200
--
-@28
-tb.uut.mprj.core1.core1.EXEC.intrq
-@1000200
--Module I/O
-@c00200
--Internal Bus
-@22
-tb.uut.mprj.core1.core1.EXEC.ibus1[31:0]
-tb.uut.mprj.core1.core1.EXEC.ibus2[31:0]
-tb.uut.mprj.core1.core1.EXEC.obus[31:0]
-tb.uut.mprj.core1.core1.EXEC.aluout[31:0]
-@1401200
--Internal Bus
-@c00200
--ALU
-@22
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv[3:0]
-@28
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv_out[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.carry
-@22
-tb.uut.mprj.core1.core1.EXEC.alu.i_a[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_b[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_op[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_r[31:0]
-@1401200
--ALU
-@c00200
--Special Registers
-@22
-tb.uut.mprj.core1.core1.EXEC.r_dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtw[31:0]
-tb.uut.mprj.core1.core1.EXEC.mar[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_u[31:0]
-tb.uut.mprj.core1.core1.EXEC.lr_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.sp_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.mcr_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.flags[31:0]
-@1401200
--Special Registers
-@c00200
--Register Control
-@28
-tb.uut.mprj.core1.core1.EXEC.reg_we
-tb.uut.mprj.core1.core1.EXEC.reg_we_s
-tb.uut.mprj.core1.core1.EXEC.reg_we_u
-@200
--
-@22
-tb.uut.mprj.core1.core1.EXEC.regadra[3:0]
-tb.uut.mprj.core1.core1.EXEC.regouta[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_u[31:0]
-@200
--
-@22
-tb.uut.mprj.core1.core1.EXEC.regadrb[3:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_u[31:0]
-@1401200
--Register Control
-@800200
--Supervisor Regfile
-@22
-tb.uut.mprj.core1.core1.EXEC.regfile_s.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[15][31:0]
-@1000200
--Supervisor Regfile
-@c00200
--User Regfile
-@22
-tb.uut.mprj.core1.core1.EXEC.regfile_u.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[15][31:0]
-@1401200
--User Regfile
--Execute
-[pattern_trace] 1
-[pattern_trace] 0

verilog/dv/caravel/hs32_soc/core1test1.no/test1.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test1.no/test1.c b/verilog/dv/caravel/hs32_soc/core1test1.no/test1.c
deleted file mode 100644
index 4a9d687..0000000
--- a/verilog/dv/caravel/hs32_soc/core1test1.no/test1.c
+++ /dev/null
@@ -1,56 +0,0 @@
-#include "../../defs.h"
-
-void main()
-{
-	// Reset
-	reg_la0_ena = 0x00000000;    // [31:0]
-	reg_la1_ena = 0xFFFFFFFF;    // [63:32]
-	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
-	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
-	
-	// Reset and control bus
-	reg_la0_data = 0b01; // [0] is high means reset
-	reg_la0_data = 0b00; // [0] is low means stop reset
-
-	// Write
-	((volatile uint32_t*) 0x30000000)[0] = 0x2400BEEF;
-	((volatile uint32_t*) 0x30000000)[1] = 0x24100ADD;
-	((volatile uint32_t*) 0x30000000)[2] = 0x20201000;
-	((volatile uint32_t*) 0x30000000)[3] = 0x60001000;
-	((volatile uint32_t*) 0x30000000)[4] = 0x30020000;
-	((volatile uint32_t*) 0x30000000)[5] = 0x10120000;
-	((volatile uint32_t*) 0x30000000)[6] = 0x24300BAD;
-	((volatile uint32_t*) 0x30000000)[7] = 0x24502262;
-	((volatile uint32_t*) 0x30000000)[8] = 0x20505800;
-	((volatile uint32_t*) 0x30000000)[9] = 0x24500000;
-	((volatile uint32_t*) 0x30000000)[10] = 0x30530000;
-	((volatile uint32_t*) 0x30000000)[11] = 0x24400BAD;
-	((volatile uint32_t*) 0x30000000)[12] = 0x24502166;
-	((volatile uint32_t*) 0x30000000)[13] = 0x20505800;
-	((volatile uint32_t*) 0x30000000)[14] = 0x24500000;
-	((volatile uint32_t*) 0x30000000)[15] = 0x30540000;
-	((volatile uint32_t*) 0x30000000)[16] = 0x68001000;
-	((volatile uint32_t*) 0x30000000)[17] = 0x52000BAD;
-	((volatile uint32_t*) 0x30000000)[18] = 0x68012000;
-	((volatile uint32_t*) 0x30000000)[19] = 0x59000B09;
-	((volatile uint32_t*) 0x30000000)[20] = 0x20706800;
-
-	// Release control and reset
-	reg_la0_data = 0b11; // [1] is high means release control back to hs32
-	reg_la0_data = 0b10;
-
-	// Configure lower 8-IOs as user output
-	// Observe counter value in the testbench
-	reg_mprj_io_0 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_1 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_2 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_3 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_4 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_5 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_6 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_7 =  GPIO_MODE_USER_STD_OUTPUT;
-
-    // Apply configuration
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-}

verilog/dv/caravel/hs32_soc/core1test1/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test1/Makefile b/verilog/dv/caravel/hs32_soc/core1test1/Makefile
index 245b54a..3bd8310 100644
--- a/verilog/dv/caravel/hs32_soc/core1test1/Makefile
+++ b/verilog/dv/caravel/hs32_soc/core1test1/Makefile
@@ -37,6 +37,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.idx
 
 .PHONY: clean hex all

verilog/dv/caravel/hs32_soc/core1test1/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test1/tb.gtkw b/verilog/dv/caravel/hs32_soc/core1test1/tb.gtkw
index 361d82b..cd40e11 100644
--- a/verilog/dv/caravel/hs32_soc/core1test1/tb.gtkw
+++ b/verilog/dv/caravel/hs32_soc/core1test1/tb.gtkw
@@ -14,8 +14,8 @@
 [treeopen] tb.uut.
 [treeopen] tb.uut.mprj.
 [treeopen] tb.uut.mprj.core1.
-[treeopen] tb.uut.mprj.core1.core1.
-[treeopen] tb.uut.mprj.core1.core1.EXEC.
+[treeopen] tb.uut.mprj.core1.core.
+[treeopen] tb.uut.mprj.core1.core.EXEC.
 [treeopen] tb.uut.mprj.sram0.
 [sst_width] 265
 [signals_width] 269
@@ -51,14 +51,14 @@
 @c00200
 -PQ
 @22
-tb.uut.mprj.core1.core1.FETCH.\fifo[0][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[1][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[2][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[3][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[4][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[5][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[6][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[7][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[0][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[1][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[2][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[3][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[4][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[5][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[6][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[7][31:0]
 @1401200
 -PQ
 @800200
@@ -104,198 +104,198 @@
 @c00200
 -Decode
 @28
-tb.uut.mprj.core1.core1.DECODE.clk
-tb.uut.mprj.core1.core1.DECODE.reset
+tb.uut.mprj.core1.core.DECODE.clk
+tb.uut.mprj.core1.core.DECODE.reset
 @22
-tb.uut.mprj.core1.core1.DECODE.int_line[23:0]
+tb.uut.mprj.core1.core.DECODE.int_line[23:0]
 @28
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.reqd
+tb.uut.mprj.core1.core.DECODE.reqd
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.rdyd
+tb.uut.mprj.core1.core.DECODE.rdyd
 @200
 -
 @28
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.reqe
+tb.uut.mprj.core1.core.DECODE.reqe
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.rdye
-tb.uut.mprj.core1.core1.DECODE.full
+tb.uut.mprj.core1.core.DECODE.rdye
+tb.uut.mprj.core1.core.DECODE.full
 @200
 -
 @22
-tb.uut.mprj.core1.core1.DECODE.instd[31:0]
+tb.uut.mprj.core1.core.DECODE.instd[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.DECODE.aluop[3:0]
+tb.uut.mprj.core1.core.DECODE.aluop[3:0]
 @28
-tb.uut.mprj.core1.core1.DECODE.bank[1:0]
+tb.uut.mprj.core1.core.DECODE.bank[1:0]
 @22
-tb.uut.mprj.core1.core1.DECODE.ctlsig[15:0]
-tb.uut.mprj.core1.core1.DECODE.imm[15:0]
-tb.uut.mprj.core1.core1.DECODE.rd[3:0]
-tb.uut.mprj.core1.core1.DECODE.rm[3:0]
-tb.uut.mprj.core1.core1.DECODE.rn[3:0]
-tb.uut.mprj.core1.core1.DECODE.shift[4:0]
+tb.uut.mprj.core1.core.DECODE.ctlsig[15:0]
+tb.uut.mprj.core1.core.DECODE.imm[15:0]
+tb.uut.mprj.core1.core.DECODE.rd[3:0]
+tb.uut.mprj.core1.core.DECODE.rm[3:0]
+tb.uut.mprj.core1.core.DECODE.rn[3:0]
+tb.uut.mprj.core1.core.DECODE.shift[4:0]
 @1401200
 -Decode
 @c00200
 -Execute
 @28
-tb.uut.mprj.core1.core1.EXEC.clk
+tb.uut.mprj.core1.core.EXEC.clk
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.req
+tb.uut.mprj.core1.core.EXEC.req
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.rdy
+tb.uut.mprj.core1.core.EXEC.rdy
 @22
-tb.uut.mprj.core1.core1.EXEC.state[3:0]
+tb.uut.mprj.core1.core.EXEC.state[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.fault
-tb.uut.mprj.core1.core1.EXEC.int_inval
+tb.uut.mprj.core1.core.EXEC.fault
+tb.uut.mprj.core1.core.EXEC.int_inval
 @c00200
 -Module I/O
 @28
-tb.uut.mprj.core1.core1.EXEC.flush
+tb.uut.mprj.core1.core.EXEC.flush
 @22
-tb.uut.mprj.core1.core1.EXEC.newpc[31:0]
+tb.uut.mprj.core1.core.EXEC.newpc[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.aluop[3:0]
-tb.uut.mprj.core1.core1.EXEC.shift[4:0]
-tb.uut.mprj.core1.core1.EXEC.imm[15:0]
-tb.uut.mprj.core1.core1.EXEC.rd[3:0]
-tb.uut.mprj.core1.core1.EXEC.rm[3:0]
-tb.uut.mprj.core1.core1.EXEC.rn[3:0]
+tb.uut.mprj.core1.core.EXEC.aluop[3:0]
+tb.uut.mprj.core1.core.EXEC.shift[4:0]
+tb.uut.mprj.core1.core.EXEC.imm[15:0]
+tb.uut.mprj.core1.core.EXEC.rd[3:0]
+tb.uut.mprj.core1.core.EXEC.rm[3:0]
+tb.uut.mprj.core1.core.EXEC.rn[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.ctlsig[15:0]
-tb.uut.mprj.core1.core1.EXEC.bank[1:0]
+tb.uut.mprj.core1.core.EXEC.ctlsig[15:0]
+tb.uut.mprj.core1.core.EXEC.bank[1:0]
 @200
 -
 @28
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.stbm
+tb.uut.mprj.core1.core.EXEC.stbm
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.ackm
+tb.uut.mprj.core1.core.EXEC.ackm
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.stlm
+tb.uut.mprj.core1.core.EXEC.stlm
 @22
-tb.uut.mprj.core1.core1.EXEC.addr[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtwm[31:0]
+tb.uut.mprj.core1.core.EXEC.addr[31:0]
+tb.uut.mprj.core1.core.EXEC.dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtwm[31:0]
 @28
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.rw_mem
+tb.uut.mprj.core1.core.EXEC.rw_mem
 @200
 -
 @28
-tb.uut.mprj.core1.core1.EXEC.intrq
+tb.uut.mprj.core1.core.EXEC.intrq
 @1401200
 -Module I/O
 @c00200
 -Internal Bus
 @22
-tb.uut.mprj.core1.core1.EXEC.ibus1[31:0]
-tb.uut.mprj.core1.core1.EXEC.ibus2[31:0]
-tb.uut.mprj.core1.core1.EXEC.obus[31:0]
-tb.uut.mprj.core1.core1.EXEC.aluout[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus1[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus2[31:0]
+tb.uut.mprj.core1.core.EXEC.obus[31:0]
+tb.uut.mprj.core1.core.EXEC.aluout[31:0]
 @1401200
 -Internal Bus
 @c00200
 -ALU
 @22
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv[3:0]
+tb.uut.mprj.core1.core.EXEC.alu_nzcv[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv_out[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.carry
+tb.uut.mprj.core1.core.EXEC.alu_nzcv_out[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.carry
 @22
-tb.uut.mprj.core1.core1.EXEC.alu.i_a[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_b[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_op[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_r[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_a[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_b[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_op[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_r[31:0]
 @1401200
 -ALU
 @c00200
 -Special Registers
 @22
-tb.uut.mprj.core1.core1.EXEC.r_dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtw[31:0]
-tb.uut.mprj.core1.core1.EXEC.mar[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_u[31:0]
-tb.uut.mprj.core1.core1.EXEC.lr_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.sp_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.mcr_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.flags[31:0]
+tb.uut.mprj.core1.core.EXEC.r_dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtw[31:0]
+tb.uut.mprj.core1.core.EXEC.mar[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_s[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_u[31:0]
+tb.uut.mprj.core1.core.EXEC.lr_i[31:0]
+tb.uut.mprj.core1.core.EXEC.sp_i[31:0]
+tb.uut.mprj.core1.core.EXEC.mcr_s[31:0]
+tb.uut.mprj.core1.core.EXEC.flags[31:0]
 @1401200
 -Special Registers
 @c00200
 -Register Control
 @28
-tb.uut.mprj.core1.core1.EXEC.reg_we
-tb.uut.mprj.core1.core1.EXEC.reg_we_s
-tb.uut.mprj.core1.core1.EXEC.reg_we_u
+tb.uut.mprj.core1.core.EXEC.reg_we
+tb.uut.mprj.core1.core.EXEC.reg_we_s
+tb.uut.mprj.core1.core.EXEC.reg_we_u
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.regadra[3:0]
-tb.uut.mprj.core1.core1.EXEC.regouta[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_u[31:0]
+tb.uut.mprj.core1.core.EXEC.regadra[3:0]
+tb.uut.mprj.core1.core.EXEC.regouta[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_u[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.regadrb[3:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_u[31:0]
+tb.uut.mprj.core1.core.EXEC.regadrb[3:0]
+tb.uut.mprj.core1.core.EXEC.regoutb[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_u[31:0]
 @1401200
 -Register Control
 @c00200
 -Supervisor Regfile
 @22
-tb.uut.mprj.core1.core1.EXEC.regfile_s.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[15][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[15][31:0]
 @1401200
 -Supervisor Regfile
 @c00200
 -User Regfile
 @22
-tb.uut.mprj.core1.core1.EXEC.regfile_u.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[15][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[15][31:0]
 @1401200
 -User Regfile
 -Execute

verilog/dv/caravel/hs32_soc/core1test1/test1_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test1/test1_tb.v b/verilog/dv/caravel/hs32_soc/core1test1/test1_tb.v
index 433d28e..eab77f8 100644
--- a/verilog/dv/caravel/hs32_soc/core1test1/test1_tb.v
+++ b/verilog/dv/caravel/hs32_soc/core1test1/test1_tb.v
@@ -8,13 +8,15 @@
 `include "spiflash.v"
 
 module tb();
+	parameter TEST_ID = 1;
+
 	reg clock;
-  reg RSTB;
+  	reg RSTB;
 	reg power1, power2;
 	reg power3, power4;
 
-  wire gpio;
-  wire [37:0] mprj_io;
+  	wire gpio;
+  	wire [37:0] mprj_io;
 	wire [7:0] mprj_io_0;
 
 	assign mprj_io_0 = mprj_io[7:0];
@@ -29,6 +31,8 @@
 		clock = 0;
 	end
 
+	reg failed = 1;
+
 	initial begin
 		$dumpfile("tb.vcd");
 		$dumpvars(0, tb);
@@ -37,9 +41,11 @@
 			repeat (1000) @(posedge clock);
 			// $display("+1000 cycles");
 		end
-		//$display("%c[1;31m",27);
-		//$display("Test 1: Failed (timed out)!");
-		//$display("%c[0m",27);
+		if(failed) begin
+			$display("%c[1;31m",27);
+			$display("Test 1: Failed (timed out)!");
+			$display("%c[0m",27);
+		end
 		$finish;
 	end
 
@@ -65,12 +71,22 @@
 	end
 
 	initial begin
-	    // Some weak test cases
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[0] == 16'hCAFE);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[1] == 16'h5);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[2] == 16'hCAFE);
-	    $display("Test 1 [MOV, LDR, STR Variant 1] Passed Weak Cases");
-	    //$finish;
+	    // MOV r0 <- 0xCAFE
+		wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[0] == 32'hCAFE);
+		// MOV r1 <- 5
+		wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[1] == 32'h5);
+		// LDR r2 <- [r1+1]
+		wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[2] == 32'hCAFE);
+		failed = 0;
+	end
+
+	always @(*) begin
+		if(tb.uut.mprj.core1.core.EXEC.fault) begin
+			$display("%c[1;31m",27);
+			$display("Test %d: Faulted!", TEST_ID);
+			$display("%c[0m",27);
+			$finish;
+		end
 	end
 
 	always @(mprj_io) begin
@@ -125,3 +141,14 @@
 	);
 endmodule
 `default_nettype wire
+
+module assert(input clk, input test);
+    always @(posedge clk)
+    begin
+        if (test !== 1)
+        begin
+            $display("ASSERTION FAILED in %m");
+            $finish;
+        end
+    end
+endmodule

verilog/dv/caravel/hs32_soc/core1test2/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test2/Makefile b/verilog/dv/caravel/hs32_soc/core1test2/Makefile
index 245b54a..d3a6346 100644
--- a/verilog/dv/caravel/hs32_soc/core1test2/Makefile
+++ b/verilog/dv/caravel/hs32_soc/core1test2/Makefile
@@ -9,7 +9,7 @@
 
 .SUFFIXES:
 
-PATTERN = test1
+PATTERN = test2
 
 all:  ${PATTERN:=.vcd}
 
@@ -37,6 +37,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.idx
 
 .PHONY: clean hex all

verilog/dv/caravel/hs32_soc/core1test2/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test2/tb.gtkw b/verilog/dv/caravel/hs32_soc/core1test2/tb.gtkw
index 361d82b..cd40e11 100644
--- a/verilog/dv/caravel/hs32_soc/core1test2/tb.gtkw
+++ b/verilog/dv/caravel/hs32_soc/core1test2/tb.gtkw
@@ -14,8 +14,8 @@
 [treeopen] tb.uut.
 [treeopen] tb.uut.mprj.
 [treeopen] tb.uut.mprj.core1.
-[treeopen] tb.uut.mprj.core1.core1.
-[treeopen] tb.uut.mprj.core1.core1.EXEC.
+[treeopen] tb.uut.mprj.core1.core.
+[treeopen] tb.uut.mprj.core1.core.EXEC.
 [treeopen] tb.uut.mprj.sram0.
 [sst_width] 265
 [signals_width] 269
@@ -51,14 +51,14 @@
 @c00200
 -PQ
 @22
-tb.uut.mprj.core1.core1.FETCH.\fifo[0][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[1][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[2][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[3][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[4][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[5][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[6][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[7][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[0][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[1][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[2][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[3][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[4][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[5][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[6][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[7][31:0]
 @1401200
 -PQ
 @800200
@@ -104,198 +104,198 @@
 @c00200
 -Decode
 @28
-tb.uut.mprj.core1.core1.DECODE.clk
-tb.uut.mprj.core1.core1.DECODE.reset
+tb.uut.mprj.core1.core.DECODE.clk
+tb.uut.mprj.core1.core.DECODE.reset
 @22
-tb.uut.mprj.core1.core1.DECODE.int_line[23:0]
+tb.uut.mprj.core1.core.DECODE.int_line[23:0]
 @28
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.reqd
+tb.uut.mprj.core1.core.DECODE.reqd
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.rdyd
+tb.uut.mprj.core1.core.DECODE.rdyd
 @200
 -
 @28
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.reqe
+tb.uut.mprj.core1.core.DECODE.reqe
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.rdye
-tb.uut.mprj.core1.core1.DECODE.full
+tb.uut.mprj.core1.core.DECODE.rdye
+tb.uut.mprj.core1.core.DECODE.full
 @200
 -
 @22
-tb.uut.mprj.core1.core1.DECODE.instd[31:0]
+tb.uut.mprj.core1.core.DECODE.instd[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.DECODE.aluop[3:0]
+tb.uut.mprj.core1.core.DECODE.aluop[3:0]
 @28
-tb.uut.mprj.core1.core1.DECODE.bank[1:0]
+tb.uut.mprj.core1.core.DECODE.bank[1:0]
 @22
-tb.uut.mprj.core1.core1.DECODE.ctlsig[15:0]
-tb.uut.mprj.core1.core1.DECODE.imm[15:0]
-tb.uut.mprj.core1.core1.DECODE.rd[3:0]
-tb.uut.mprj.core1.core1.DECODE.rm[3:0]
-tb.uut.mprj.core1.core1.DECODE.rn[3:0]
-tb.uut.mprj.core1.core1.DECODE.shift[4:0]
+tb.uut.mprj.core1.core.DECODE.ctlsig[15:0]
+tb.uut.mprj.core1.core.DECODE.imm[15:0]
+tb.uut.mprj.core1.core.DECODE.rd[3:0]
+tb.uut.mprj.core1.core.DECODE.rm[3:0]
+tb.uut.mprj.core1.core.DECODE.rn[3:0]
+tb.uut.mprj.core1.core.DECODE.shift[4:0]
 @1401200
 -Decode
 @c00200
 -Execute
 @28
-tb.uut.mprj.core1.core1.EXEC.clk
+tb.uut.mprj.core1.core.EXEC.clk
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.req
+tb.uut.mprj.core1.core.EXEC.req
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.rdy
+tb.uut.mprj.core1.core.EXEC.rdy
 @22
-tb.uut.mprj.core1.core1.EXEC.state[3:0]
+tb.uut.mprj.core1.core.EXEC.state[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.fault
-tb.uut.mprj.core1.core1.EXEC.int_inval
+tb.uut.mprj.core1.core.EXEC.fault
+tb.uut.mprj.core1.core.EXEC.int_inval
 @c00200
 -Module I/O
 @28
-tb.uut.mprj.core1.core1.EXEC.flush
+tb.uut.mprj.core1.core.EXEC.flush
 @22
-tb.uut.mprj.core1.core1.EXEC.newpc[31:0]
+tb.uut.mprj.core1.core.EXEC.newpc[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.aluop[3:0]
-tb.uut.mprj.core1.core1.EXEC.shift[4:0]
-tb.uut.mprj.core1.core1.EXEC.imm[15:0]
-tb.uut.mprj.core1.core1.EXEC.rd[3:0]
-tb.uut.mprj.core1.core1.EXEC.rm[3:0]
-tb.uut.mprj.core1.core1.EXEC.rn[3:0]
+tb.uut.mprj.core1.core.EXEC.aluop[3:0]
+tb.uut.mprj.core1.core.EXEC.shift[4:0]
+tb.uut.mprj.core1.core.EXEC.imm[15:0]
+tb.uut.mprj.core1.core.EXEC.rd[3:0]
+tb.uut.mprj.core1.core.EXEC.rm[3:0]
+tb.uut.mprj.core1.core.EXEC.rn[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.ctlsig[15:0]
-tb.uut.mprj.core1.core1.EXEC.bank[1:0]
+tb.uut.mprj.core1.core.EXEC.ctlsig[15:0]
+tb.uut.mprj.core1.core.EXEC.bank[1:0]
 @200
 -
 @28
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.stbm
+tb.uut.mprj.core1.core.EXEC.stbm
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.ackm
+tb.uut.mprj.core1.core.EXEC.ackm
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.stlm
+tb.uut.mprj.core1.core.EXEC.stlm
 @22
-tb.uut.mprj.core1.core1.EXEC.addr[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtwm[31:0]
+tb.uut.mprj.core1.core.EXEC.addr[31:0]
+tb.uut.mprj.core1.core.EXEC.dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtwm[31:0]
 @28
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.rw_mem
+tb.uut.mprj.core1.core.EXEC.rw_mem
 @200
 -
 @28
-tb.uut.mprj.core1.core1.EXEC.intrq
+tb.uut.mprj.core1.core.EXEC.intrq
 @1401200
 -Module I/O
 @c00200
 -Internal Bus
 @22
-tb.uut.mprj.core1.core1.EXEC.ibus1[31:0]
-tb.uut.mprj.core1.core1.EXEC.ibus2[31:0]
-tb.uut.mprj.core1.core1.EXEC.obus[31:0]
-tb.uut.mprj.core1.core1.EXEC.aluout[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus1[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus2[31:0]
+tb.uut.mprj.core1.core.EXEC.obus[31:0]
+tb.uut.mprj.core1.core.EXEC.aluout[31:0]
 @1401200
 -Internal Bus
 @c00200
 -ALU
 @22
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv[3:0]
+tb.uut.mprj.core1.core.EXEC.alu_nzcv[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv_out[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.carry
+tb.uut.mprj.core1.core.EXEC.alu_nzcv_out[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.carry
 @22
-tb.uut.mprj.core1.core1.EXEC.alu.i_a[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_b[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_op[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_r[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_a[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_b[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_op[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_r[31:0]
 @1401200
 -ALU
 @c00200
 -Special Registers
 @22
-tb.uut.mprj.core1.core1.EXEC.r_dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtw[31:0]
-tb.uut.mprj.core1.core1.EXEC.mar[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_u[31:0]
-tb.uut.mprj.core1.core1.EXEC.lr_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.sp_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.mcr_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.flags[31:0]
+tb.uut.mprj.core1.core.EXEC.r_dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtw[31:0]
+tb.uut.mprj.core1.core.EXEC.mar[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_s[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_u[31:0]
+tb.uut.mprj.core1.core.EXEC.lr_i[31:0]
+tb.uut.mprj.core1.core.EXEC.sp_i[31:0]
+tb.uut.mprj.core1.core.EXEC.mcr_s[31:0]
+tb.uut.mprj.core1.core.EXEC.flags[31:0]
 @1401200
 -Special Registers
 @c00200
 -Register Control
 @28
-tb.uut.mprj.core1.core1.EXEC.reg_we
-tb.uut.mprj.core1.core1.EXEC.reg_we_s
-tb.uut.mprj.core1.core1.EXEC.reg_we_u
+tb.uut.mprj.core1.core.EXEC.reg_we
+tb.uut.mprj.core1.core.EXEC.reg_we_s
+tb.uut.mprj.core1.core.EXEC.reg_we_u
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.regadra[3:0]
-tb.uut.mprj.core1.core1.EXEC.regouta[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_u[31:0]
+tb.uut.mprj.core1.core.EXEC.regadra[3:0]
+tb.uut.mprj.core1.core.EXEC.regouta[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_u[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.regadrb[3:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_u[31:0]
+tb.uut.mprj.core1.core.EXEC.regadrb[3:0]
+tb.uut.mprj.core1.core.EXEC.regoutb[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_u[31:0]
 @1401200
 -Register Control
 @c00200
 -Supervisor Regfile
 @22
-tb.uut.mprj.core1.core1.EXEC.regfile_s.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[15][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[15][31:0]
 @1401200
 -Supervisor Regfile
 @c00200
 -User Regfile
 @22
-tb.uut.mprj.core1.core1.EXEC.regfile_u.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[15][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[15][31:0]
 @1401200
 -User Regfile
 -Execute

verilog/dv/caravel/hs32_soc/core1test2/test2.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test2/test1.c b/verilog/dv/caravel/hs32_soc/core1test2/test2.c
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test2/test1.c
rename to verilog/dv/caravel/hs32_soc/core1test2/test2.c

verilog/dv/caravel/hs32_soc/core1test2/test2_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v b/verilog/dv/caravel/hs32_soc/core1test2/test2_tb.v
similarity index 84%
copy from verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v
copy to verilog/dv/caravel/hs32_soc/core1test2/test2_tb.v
index 433d28e..4be79dc 100644
--- a/verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v
+++ b/verilog/dv/caravel/hs32_soc/core1test2/test2_tb.v
@@ -8,13 +8,15 @@
 `include "spiflash.v"
 
 module tb();
+	parameter TEST_ID = 2;
+
 	reg clock;
-  reg RSTB;
+  	reg RSTB;
 	reg power1, power2;
 	reg power3, power4;
 
-  wire gpio;
-  wire [37:0] mprj_io;
+  	wire gpio;
+  	wire [37:0] mprj_io;
 	wire [7:0] mprj_io_0;
 
 	assign mprj_io_0 = mprj_io[7:0];
@@ -65,12 +67,16 @@
 	end
 
 	initial begin
-	    // Some weak test cases
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[0] == 16'hCAFE);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[1] == 16'h5);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[2] == 16'hCAFE);
-	    $display("Test 1 [MOV, LDR, STR Variant 1] Passed Weak Cases");
-	    //$finish;
+	    // Test cases go here
+	end
+
+	always @(*) begin
+		if(tb.uut.mprj.core1.core.EXEC.fault) begin
+			$display("%c[1;31m",27);
+			$display("Test %d: Faulted!", TEST_ID);
+			$display("%c[0m",27);
+			$finish;
+		end
 	end
 
 	always @(mprj_io) begin
@@ -114,7 +120,7 @@
 	);
 
 	spiflash #(
-		.FILENAME("test1.hex")
+		.FILENAME("test2.hex")
 	) spiflash (
 		.csb(flash_csb),
 		.clk(flash_clk),

verilog/dv/caravel/hs32_soc/core1test3/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test3/Makefile b/verilog/dv/caravel/hs32_soc/core1test3/Makefile
index 245b54a..8265b9d 100644
--- a/verilog/dv/caravel/hs32_soc/core1test3/Makefile
+++ b/verilog/dv/caravel/hs32_soc/core1test3/Makefile
@@ -9,7 +9,7 @@
 
 .SUFFIXES:
 
-PATTERN = test1
+PATTERN = test3
 
 all:  ${PATTERN:=.vcd}
 
@@ -37,6 +37,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.idx
 
 .PHONY: clean hex all

verilog/dv/caravel/hs32_soc/core1test3/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test3/README.md b/verilog/dv/caravel/hs32_soc/core1test3/README.md
index 1f31033..40f7a48 100644
--- a/verilog/dv/caravel/hs32_soc/core1test3/README.md
+++ b/verilog/dv/caravel/hs32_soc/core1test3/README.md
@@ -64,8 +64,8 @@
 - [x] `R3   = 0x00F0`
 - [x] `R4   = 0x0F00`
 - [x] `R5   = 0xF000`
-- [x] `R6   = 0xF000`
+- [x] `R6   = 0xF001`
 - [x] `R1_u = 0x000F`
 - [x] `R2_s = 0x00F0`
-- [ ] `R3_i = 0x0F00`
+- [x] `R3_i = 0x0F00`
 - [x] `R5_f = 0xF000`

verilog/dv/caravel/hs32_soc/core1test3/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test3/tb.gtkw b/verilog/dv/caravel/hs32_soc/core1test3/tb.gtkw
index 361d82b..2efb71f 100644
--- a/verilog/dv/caravel/hs32_soc/core1test3/tb.gtkw
+++ b/verilog/dv/caravel/hs32_soc/core1test3/tb.gtkw
@@ -1,26 +1,25 @@
 [*]
 [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
-[*] Thu Dec 17 01:48:51 2020
+[*] Fri Dec 18 02:59:09 2020
 [*]
-[dumpfile] "/data/caravel-hs32core/verilog/dv/caravel/hs32_soc/core1test2/dump.vcd"
-[dumpfile_mtime] "Thu Dec 17 00:46:37 2020"
-[dumpfile_size] 322055879
-[savefile] "/data/caravel-hs32core/verilog/dv/caravel/hs32_soc/core1test2/tb.gtkw"
-[timestart] 131606720
+[dumpfile] "/data/caravel-hs32core/verilog/dv/caravel/hs32_soc/core1test3/dump.vcd"
+[dumpfile_mtime] "Fri Dec 18 02:51:43 2020"
+[dumpfile_size] 334713122
+[savefile] "/data/caravel-hs32core/verilog/dv/caravel/hs32_soc/core1test3/tb.gtkw"
+[timestart] 177719800
 [size] 1536 801
 [pos] -9 -33
-*-14.106964 131652000 131484000 131676000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-16.106964 177900000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] tb.
 [treeopen] tb.uut.
 [treeopen] tb.uut.mprj.
 [treeopen] tb.uut.mprj.core1.
-[treeopen] tb.uut.mprj.core1.core1.
-[treeopen] tb.uut.mprj.core1.core1.EXEC.
+[treeopen] tb.uut.mprj.core1.core.
 [treeopen] tb.uut.mprj.sram0.
 [sst_width] 265
 [signals_width] 269
 [sst_expanded] 1
-[sst_vpaned_height] 222
+[sst_vpaned_height] 301
 @c00200
 -WBS
 @28
@@ -51,17 +50,17 @@
 @c00200
 -PQ
 @22
-tb.uut.mprj.core1.core1.FETCH.\fifo[0][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[1][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[2][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[3][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[4][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[5][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[6][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[7][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[0][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[1][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[2][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[3][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[4][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[5][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[6][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[7][31:0]
 @1401200
 -PQ
-@800200
+@c00200
 -BRAM CTL
 @22
 tb.uut.mprj.core1.bram_ctl.i_addr[11:0]
@@ -99,205 +98,208 @@
 tb.uut.mprj.core1.bram_ctl.dbuf1[31:0]
 tb.uut.mprj.core1.bram_ctl.dbuf2[31:0]
 tb.uut.mprj.core1.bram_ctl.dbuf3[31:0]
-@1000200
+@1401200
 -BRAM CTL
 @c00200
 -Decode
 @28
-tb.uut.mprj.core1.core1.DECODE.clk
-tb.uut.mprj.core1.core1.DECODE.reset
+tb.uut.mprj.core1.core.DECODE.clk
+tb.uut.mprj.core1.core.DECODE.reset
 @22
-tb.uut.mprj.core1.core1.DECODE.int_line[23:0]
+tb.uut.mprj.core1.core.DECODE.int_line[23:0]
 @28
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.reqd
+tb.uut.mprj.core1.core.DECODE.reqd
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.rdyd
+tb.uut.mprj.core1.core.DECODE.rdyd
 @200
 -
 @28
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.reqe
+tb.uut.mprj.core1.core.DECODE.reqe
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.rdye
-tb.uut.mprj.core1.core1.DECODE.full
+tb.uut.mprj.core1.core.DECODE.rdye
+tb.uut.mprj.core1.core.DECODE.full
 @200
 -
 @22
-tb.uut.mprj.core1.core1.DECODE.instd[31:0]
+tb.uut.mprj.core1.core.DECODE.instd[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.DECODE.aluop[3:0]
+tb.uut.mprj.core1.core.DECODE.aluop[3:0]
 @28
-tb.uut.mprj.core1.core1.DECODE.bank[1:0]
+tb.uut.mprj.core1.core.DECODE.bank[1:0]
 @22
-tb.uut.mprj.core1.core1.DECODE.ctlsig[15:0]
-tb.uut.mprj.core1.core1.DECODE.imm[15:0]
-tb.uut.mprj.core1.core1.DECODE.rd[3:0]
-tb.uut.mprj.core1.core1.DECODE.rm[3:0]
-tb.uut.mprj.core1.core1.DECODE.rn[3:0]
-tb.uut.mprj.core1.core1.DECODE.shift[4:0]
+tb.uut.mprj.core1.core.DECODE.ctlsig[15:0]
+tb.uut.mprj.core1.core.DECODE.imm[15:0]
+tb.uut.mprj.core1.core.DECODE.rd[3:0]
+tb.uut.mprj.core1.core.DECODE.rm[3:0]
+tb.uut.mprj.core1.core.DECODE.rn[3:0]
+tb.uut.mprj.core1.core.DECODE.shift[4:0]
 @1401200
 -Decode
-@c00200
+@800200
 -Execute
 @28
-tb.uut.mprj.core1.core1.EXEC.clk
+tb.uut.mprj.core1.core.EXEC.clk
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.req
+tb.uut.mprj.core1.core.EXEC.req
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.rdy
+tb.uut.mprj.core1.core.EXEC.rdy
 @22
-tb.uut.mprj.core1.core1.EXEC.state[3:0]
+tb.uut.mprj.core1.core.EXEC.state[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.fault
-tb.uut.mprj.core1.core1.EXEC.int_inval
+tb.uut.mprj.core1.core.EXEC.fault
+tb.uut.mprj.core1.core.EXEC.int_inval
 @c00200
 -Module I/O
 @28
-tb.uut.mprj.core1.core1.EXEC.flush
+tb.uut.mprj.core1.core.EXEC.flush
 @22
-tb.uut.mprj.core1.core1.EXEC.newpc[31:0]
+tb.uut.mprj.core1.core.EXEC.newpc[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.aluop[3:0]
-tb.uut.mprj.core1.core1.EXEC.shift[4:0]
-tb.uut.mprj.core1.core1.EXEC.imm[15:0]
-tb.uut.mprj.core1.core1.EXEC.rd[3:0]
-tb.uut.mprj.core1.core1.EXEC.rm[3:0]
-tb.uut.mprj.core1.core1.EXEC.rn[3:0]
+tb.uut.mprj.core1.core.EXEC.aluop[3:0]
+tb.uut.mprj.core1.core.EXEC.shift[4:0]
+tb.uut.mprj.core1.core.EXEC.imm[15:0]
+tb.uut.mprj.core1.core.EXEC.rd[3:0]
+tb.uut.mprj.core1.core.EXEC.rm[3:0]
+tb.uut.mprj.core1.core.EXEC.rn[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.ctlsig[15:0]
-tb.uut.mprj.core1.core1.EXEC.bank[1:0]
+tb.uut.mprj.core1.core.EXEC.ctlsig[15:0]
+tb.uut.mprj.core1.core.EXEC.bank[1:0]
 @200
 -
 @28
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.stbm
+tb.uut.mprj.core1.core.EXEC.stbm
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.ackm
+tb.uut.mprj.core1.core.EXEC.ackm
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.stlm
+tb.uut.mprj.core1.core.EXEC.stlm
 @22
-tb.uut.mprj.core1.core1.EXEC.addr[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtwm[31:0]
+tb.uut.mprj.core1.core.EXEC.addr[31:0]
+tb.uut.mprj.core1.core.EXEC.dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtwm[31:0]
 @28
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.rw_mem
+tb.uut.mprj.core1.core.EXEC.rw_mem
 @200
 -
 @28
-tb.uut.mprj.core1.core1.EXEC.intrq
+tb.uut.mprj.core1.core.EXEC.intrq
 @1401200
 -Module I/O
 @c00200
 -Internal Bus
 @22
-tb.uut.mprj.core1.core1.EXEC.ibus1[31:0]
-tb.uut.mprj.core1.core1.EXEC.ibus2[31:0]
-tb.uut.mprj.core1.core1.EXEC.obus[31:0]
-tb.uut.mprj.core1.core1.EXEC.aluout[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus1[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus2[31:0]
+tb.uut.mprj.core1.core.EXEC.obus[31:0]
+tb.uut.mprj.core1.core.EXEC.aluout[31:0]
 @1401200
 -Internal Bus
-@c00200
+@800200
 -ALU
 @22
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv[3:0]
+tb.uut.mprj.core1.core.EXEC.alu_nzcv[3:0]
+tb.uut.mprj.core1.core.EXEC.branch_conds[15:0]
+@29
+tb.uut.mprj.core1.core.EXEC.alu_nzcv_out[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv_out[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.carry
+tb.uut.mprj.core1.core.EXEC.alu.carry
 @22
-tb.uut.mprj.core1.core1.EXEC.alu.i_a[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_b[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_op[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_r[31:0]
-@1401200
+tb.uut.mprj.core1.core.EXEC.alu.i_a[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_b[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_op[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_r[31:0]
+@1000200
 -ALU
-@c00200
+@800200
 -Special Registers
 @22
-tb.uut.mprj.core1.core1.EXEC.r_dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtw[31:0]
-tb.uut.mprj.core1.core1.EXEC.mar[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_u[31:0]
-tb.uut.mprj.core1.core1.EXEC.lr_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.sp_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.mcr_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.flags[31:0]
-@1401200
+tb.uut.mprj.core1.core.EXEC.r_dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtw[31:0]
+tb.uut.mprj.core1.core.EXEC.mar[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_s[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_u[31:0]
+tb.uut.mprj.core1.core.EXEC.lr_i[31:0]
+tb.uut.mprj.core1.core.EXEC.sp_i[31:0]
+tb.uut.mprj.core1.core.EXEC.mcr_s[31:0]
+tb.uut.mprj.core1.core.EXEC.flags[31:0]
+@1000200
 -Special Registers
 @c00200
 -Register Control
 @28
-tb.uut.mprj.core1.core1.EXEC.reg_we
-tb.uut.mprj.core1.core1.EXEC.reg_we_s
-tb.uut.mprj.core1.core1.EXEC.reg_we_u
+tb.uut.mprj.core1.core.EXEC.reg_we
+tb.uut.mprj.core1.core.EXEC.reg_we_s
+tb.uut.mprj.core1.core.EXEC.reg_we_u
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.regadra[3:0]
-tb.uut.mprj.core1.core1.EXEC.regouta[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_u[31:0]
+tb.uut.mprj.core1.core.EXEC.regadra[3:0]
+tb.uut.mprj.core1.core.EXEC.regouta[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_u[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.regadrb[3:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_u[31:0]
+tb.uut.mprj.core1.core.EXEC.regadrb[3:0]
+tb.uut.mprj.core1.core.EXEC.regoutb[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_u[31:0]
 @1401200
 -Register Control
 @c00200
 -Supervisor Regfile
 @22
-tb.uut.mprj.core1.core1.EXEC.regfile_s.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[15][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[15][31:0]
 @1401200
 -Supervisor Regfile
 @c00200
 -User Regfile
 @22
-tb.uut.mprj.core1.core1.EXEC.regfile_u.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[15][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[15][31:0]
 @1401200
 -User Regfile
+@1000200
 -Execute
 @c00200
 -sram0
@@ -330,7 +332,7 @@
 tb.uut.mprj.sram1.wmask0[3:0]
 @1401200
 -sram1
-@800200
+@c00200
 -sram3
 @22
 tb.uut.mprj.sram2.addr0[7:0]
@@ -343,7 +345,7 @@
 @28
 tb.uut.mprj.sram2.web0
 tb.uut.mprj.sram2.wmask0[3:0]
-@1000200
+@1401200
 -sram3
 [pattern_trace] 1
 [pattern_trace] 0

verilog/dv/caravel/hs32_soc/core1test3/test1_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test3/test1_tb.v b/verilog/dv/caravel/hs32_soc/core1test3/test1_tb.v
deleted file mode 100644
index 433d28e..0000000
--- a/verilog/dv/caravel/hs32_soc/core1test3/test1_tb.v
+++ /dev/null
@@ -1,127 +0,0 @@
-`define DBG1
-
-`default_nettype none
-
-`timescale 1 ns / 1 ns
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module tb();
-	reg clock;
-  reg RSTB;
-	reg power1, power2;
-	reg power3, power4;
-
-  wire gpio;
-  wire [37:0] mprj_io;
-	wire [7:0] mprj_io_0;
-
-	assign mprj_io_0 = mprj_io[7:0];
-
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #12 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin
-		$dumpfile("tb.vcd");
-		$dumpvars(0, tb);
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (25) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
-		//$display("%c[1;31m",27);
-		//$display("Test 1: Failed (timed out)!");
-		//$display("%c[0m",27);
-		$finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		#2000;
-		RSTB <= 1'b1;	    // Release reset
-	end
-
-	initial begin			// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		power3 <= 1'b0;
-		power4 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-		#200;
-		power3 <= 1'b1;
-		#200;
-		power4 <= 1'b1;
-	end
-
-	initial begin
-	    // Some weak test cases
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[0] == 16'hCAFE);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[1] == 16'h5);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[2] == 16'hCAFE);
-	    $display("Test 1 [MOV, LDR, STR Variant 1] Passed Weak Cases");
-	    //$finish;
-	end
-
-	always @(mprj_io) begin
-		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
-	end
-
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-
-	wire VDD3V3 = power1;
-	wire VDD1V8 = power2;
-	wire USER_VDD3V3 = power3;
-	wire USER_VDD1V8 = power4;
-	wire VSS = 1'b0;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (USER_VDD3V3),
-		.vdda2    (USER_VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (USER_VDD1V8),
-		.vccd2	  (USER_VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-        .mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("test1.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-endmodule
-`default_nettype wire

verilog/dv/caravel/hs32_soc/core1test3/test3.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test3/test1.c b/verilog/dv/caravel/hs32_soc/core1test3/test3.c
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test3/test1.c
rename to verilog/dv/caravel/hs32_soc/core1test3/test3.c

verilog/dv/caravel/hs32_soc/core1test3/test3_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test1.no/test1_tb.v b/verilog/dv/caravel/hs32_soc/core1test3/test3_tb.v
similarity index 93%
rename from verilog/dv/caravel/hs32_soc/core1test1.no/test1_tb.v
rename to verilog/dv/caravel/hs32_soc/core1test3/test3_tb.v
index d73c543..7e94c3a 100644
--- a/verilog/dv/caravel/hs32_soc/core1test1.no/test1_tb.v
+++ b/verilog/dv/caravel/hs32_soc/core1test3/test3_tb.v
@@ -32,14 +32,13 @@
 	initial begin
 		$dumpfile("tb.vcd");
 		$dumpvars(0, tb);
-
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
 		repeat (25) begin
 			repeat (1000) @(posedge clock);
 			// $display("+1000 cycles");
 		end
 		//$display("%c[1;31m",27);
-		//$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+		//$display("Test 1: Failed (timed out)!");
 		//$display("%c[0m",27);
 		$finish;
 	end
@@ -50,7 +49,7 @@
 		RSTB <= 1'b1;	    // Release reset
 	end
 
-	initial begin		// Power-up sequence
+	initial begin			// Power-up sequence
 		power1 <= 1'b0;
 		power2 <= 1'b0;
 		power3 <= 1'b0;
@@ -106,7 +105,7 @@
 	);
 
 	spiflash #(
-		.FILENAME("test1.hex")
+		.FILENAME("test3.hex")
 	) spiflash (
 		.csb(flash_csb),
 		.clk(flash_clk),

verilog/dv/caravel/hs32_soc/core1test4/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test4/Makefile b/verilog/dv/caravel/hs32_soc/core1test4/Makefile
index 245b54a..a2f250a 100644
--- a/verilog/dv/caravel/hs32_soc/core1test4/Makefile
+++ b/verilog/dv/caravel/hs32_soc/core1test4/Makefile
@@ -9,7 +9,7 @@
 
 .SUFFIXES:
 
-PATTERN = test1
+PATTERN = test4
 
 all:  ${PATTERN:=.vcd}
 
@@ -37,6 +37,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.idx
 
 .PHONY: clean hex all

verilog/dv/caravel/hs32_soc/core1test4/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test4/README.md b/verilog/dv/caravel/hs32_soc/core1test4/README.md
index 32024b6..fa3ecde 100644
--- a/verilog/dv/caravel/hs32_soc/core1test4/README.md
+++ b/verilog/dv/caravel/hs32_soc/core1test4/README.md
@@ -63,4 +63,28 @@
 - [x] `R4   = 0x0BAD`
 - [x] `R5   = 0x0B09`
 - [x] `R6   = 0x000F`
-- [ ] `R7   = 0x0F00`
+- [x] `R7   = 0x0F00`
+
+
+
+0x 24 00 BE EF
+0x 24 10 0A DD
+0x 20 20 10 00
+0x 60 00 10 00
+0x 30 02 00 00
+0x 10 12 00 00
+0x 24 30 0B AD
+0x 24 50 22 62
+0x 20 50 58 00
+0x 24 50 00 00
+0x 30 53 00 00
+0x 24 40 0B AD
+0x 24 50 21 66
+0x 20 50 58 00
+0x 24 50 00 00
+0x 30 54 00 00
+0x 68 00 10 00
+0x 52 00 0B AD
+0x 68 01 20 00
+0x 59 00 0B 09
+0x 20 70 68 00
\ No newline at end of file

verilog/dv/caravel/hs32_soc/core1test4/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test4/tb.gtkw b/verilog/dv/caravel/hs32_soc/core1test4/tb.gtkw
index 361d82b..cd40e11 100644
--- a/verilog/dv/caravel/hs32_soc/core1test4/tb.gtkw
+++ b/verilog/dv/caravel/hs32_soc/core1test4/tb.gtkw
@@ -14,8 +14,8 @@
 [treeopen] tb.uut.
 [treeopen] tb.uut.mprj.
 [treeopen] tb.uut.mprj.core1.
-[treeopen] tb.uut.mprj.core1.core1.
-[treeopen] tb.uut.mprj.core1.core1.EXEC.
+[treeopen] tb.uut.mprj.core1.core.
+[treeopen] tb.uut.mprj.core1.core.EXEC.
 [treeopen] tb.uut.mprj.sram0.
 [sst_width] 265
 [signals_width] 269
@@ -51,14 +51,14 @@
 @c00200
 -PQ
 @22
-tb.uut.mprj.core1.core1.FETCH.\fifo[0][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[1][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[2][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[3][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[4][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[5][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[6][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[7][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[0][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[1][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[2][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[3][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[4][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[5][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[6][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[7][31:0]
 @1401200
 -PQ
 @800200
@@ -104,198 +104,198 @@
 @c00200
 -Decode
 @28
-tb.uut.mprj.core1.core1.DECODE.clk
-tb.uut.mprj.core1.core1.DECODE.reset
+tb.uut.mprj.core1.core.DECODE.clk
+tb.uut.mprj.core1.core.DECODE.reset
 @22
-tb.uut.mprj.core1.core1.DECODE.int_line[23:0]
+tb.uut.mprj.core1.core.DECODE.int_line[23:0]
 @28
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.reqd
+tb.uut.mprj.core1.core.DECODE.reqd
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.rdyd
+tb.uut.mprj.core1.core.DECODE.rdyd
 @200
 -
 @28
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.reqe
+tb.uut.mprj.core1.core.DECODE.reqe
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.rdye
-tb.uut.mprj.core1.core1.DECODE.full
+tb.uut.mprj.core1.core.DECODE.rdye
+tb.uut.mprj.core1.core.DECODE.full
 @200
 -
 @22
-tb.uut.mprj.core1.core1.DECODE.instd[31:0]
+tb.uut.mprj.core1.core.DECODE.instd[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.DECODE.aluop[3:0]
+tb.uut.mprj.core1.core.DECODE.aluop[3:0]
 @28
-tb.uut.mprj.core1.core1.DECODE.bank[1:0]
+tb.uut.mprj.core1.core.DECODE.bank[1:0]
 @22
-tb.uut.mprj.core1.core1.DECODE.ctlsig[15:0]
-tb.uut.mprj.core1.core1.DECODE.imm[15:0]
-tb.uut.mprj.core1.core1.DECODE.rd[3:0]
-tb.uut.mprj.core1.core1.DECODE.rm[3:0]
-tb.uut.mprj.core1.core1.DECODE.rn[3:0]
-tb.uut.mprj.core1.core1.DECODE.shift[4:0]
+tb.uut.mprj.core1.core.DECODE.ctlsig[15:0]
+tb.uut.mprj.core1.core.DECODE.imm[15:0]
+tb.uut.mprj.core1.core.DECODE.rd[3:0]
+tb.uut.mprj.core1.core.DECODE.rm[3:0]
+tb.uut.mprj.core1.core.DECODE.rn[3:0]
+tb.uut.mprj.core1.core.DECODE.shift[4:0]
 @1401200
 -Decode
 @c00200
 -Execute
 @28
-tb.uut.mprj.core1.core1.EXEC.clk
+tb.uut.mprj.core1.core.EXEC.clk
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.req
+tb.uut.mprj.core1.core.EXEC.req
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.rdy
+tb.uut.mprj.core1.core.EXEC.rdy
 @22
-tb.uut.mprj.core1.core1.EXEC.state[3:0]
+tb.uut.mprj.core1.core.EXEC.state[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.fault
-tb.uut.mprj.core1.core1.EXEC.int_inval
+tb.uut.mprj.core1.core.EXEC.fault
+tb.uut.mprj.core1.core.EXEC.int_inval
 @c00200
 -Module I/O
 @28
-tb.uut.mprj.core1.core1.EXEC.flush
+tb.uut.mprj.core1.core.EXEC.flush
 @22
-tb.uut.mprj.core1.core1.EXEC.newpc[31:0]
+tb.uut.mprj.core1.core.EXEC.newpc[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.aluop[3:0]
-tb.uut.mprj.core1.core1.EXEC.shift[4:0]
-tb.uut.mprj.core1.core1.EXEC.imm[15:0]
-tb.uut.mprj.core1.core1.EXEC.rd[3:0]
-tb.uut.mprj.core1.core1.EXEC.rm[3:0]
-tb.uut.mprj.core1.core1.EXEC.rn[3:0]
+tb.uut.mprj.core1.core.EXEC.aluop[3:0]
+tb.uut.mprj.core1.core.EXEC.shift[4:0]
+tb.uut.mprj.core1.core.EXEC.imm[15:0]
+tb.uut.mprj.core1.core.EXEC.rd[3:0]
+tb.uut.mprj.core1.core.EXEC.rm[3:0]
+tb.uut.mprj.core1.core.EXEC.rn[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.ctlsig[15:0]
-tb.uut.mprj.core1.core1.EXEC.bank[1:0]
+tb.uut.mprj.core1.core.EXEC.ctlsig[15:0]
+tb.uut.mprj.core1.core.EXEC.bank[1:0]
 @200
 -
 @28
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.stbm
+tb.uut.mprj.core1.core.EXEC.stbm
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.ackm
+tb.uut.mprj.core1.core.EXEC.ackm
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.stlm
+tb.uut.mprj.core1.core.EXEC.stlm
 @22
-tb.uut.mprj.core1.core1.EXEC.addr[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtwm[31:0]
+tb.uut.mprj.core1.core.EXEC.addr[31:0]
+tb.uut.mprj.core1.core.EXEC.dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtwm[31:0]
 @28
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.rw_mem
+tb.uut.mprj.core1.core.EXEC.rw_mem
 @200
 -
 @28
-tb.uut.mprj.core1.core1.EXEC.intrq
+tb.uut.mprj.core1.core.EXEC.intrq
 @1401200
 -Module I/O
 @c00200
 -Internal Bus
 @22
-tb.uut.mprj.core1.core1.EXEC.ibus1[31:0]
-tb.uut.mprj.core1.core1.EXEC.ibus2[31:0]
-tb.uut.mprj.core1.core1.EXEC.obus[31:0]
-tb.uut.mprj.core1.core1.EXEC.aluout[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus1[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus2[31:0]
+tb.uut.mprj.core1.core.EXEC.obus[31:0]
+tb.uut.mprj.core1.core.EXEC.aluout[31:0]
 @1401200
 -Internal Bus
 @c00200
 -ALU
 @22
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv[3:0]
+tb.uut.mprj.core1.core.EXEC.alu_nzcv[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv_out[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.carry
+tb.uut.mprj.core1.core.EXEC.alu_nzcv_out[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.carry
 @22
-tb.uut.mprj.core1.core1.EXEC.alu.i_a[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_b[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_op[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_r[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_a[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_b[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_op[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_r[31:0]
 @1401200
 -ALU
 @c00200
 -Special Registers
 @22
-tb.uut.mprj.core1.core1.EXEC.r_dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtw[31:0]
-tb.uut.mprj.core1.core1.EXEC.mar[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_u[31:0]
-tb.uut.mprj.core1.core1.EXEC.lr_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.sp_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.mcr_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.flags[31:0]
+tb.uut.mprj.core1.core.EXEC.r_dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtw[31:0]
+tb.uut.mprj.core1.core.EXEC.mar[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_s[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_u[31:0]
+tb.uut.mprj.core1.core.EXEC.lr_i[31:0]
+tb.uut.mprj.core1.core.EXEC.sp_i[31:0]
+tb.uut.mprj.core1.core.EXEC.mcr_s[31:0]
+tb.uut.mprj.core1.core.EXEC.flags[31:0]
 @1401200
 -Special Registers
 @c00200
 -Register Control
 @28
-tb.uut.mprj.core1.core1.EXEC.reg_we
-tb.uut.mprj.core1.core1.EXEC.reg_we_s
-tb.uut.mprj.core1.core1.EXEC.reg_we_u
+tb.uut.mprj.core1.core.EXEC.reg_we
+tb.uut.mprj.core1.core.EXEC.reg_we_s
+tb.uut.mprj.core1.core.EXEC.reg_we_u
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.regadra[3:0]
-tb.uut.mprj.core1.core1.EXEC.regouta[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_u[31:0]
+tb.uut.mprj.core1.core.EXEC.regadra[3:0]
+tb.uut.mprj.core1.core.EXEC.regouta[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_u[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.regadrb[3:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_u[31:0]
+tb.uut.mprj.core1.core.EXEC.regadrb[3:0]
+tb.uut.mprj.core1.core.EXEC.regoutb[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_u[31:0]
 @1401200
 -Register Control
 @c00200
 -Supervisor Regfile
 @22
-tb.uut.mprj.core1.core1.EXEC.regfile_s.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[15][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[15][31:0]
 @1401200
 -Supervisor Regfile
 @c00200
 -User Regfile
 @22
-tb.uut.mprj.core1.core1.EXEC.regfile_u.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[15][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[15][31:0]
 @1401200
 -User Regfile
 -Execute

verilog/dv/caravel/hs32_soc/core1test4/test4.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test4/test1.c b/verilog/dv/caravel/hs32_soc/core1test4/test4.c
similarity index 100%
rename from verilog/dv/caravel/hs32_soc/core1test4/test1.c
rename to verilog/dv/caravel/hs32_soc/core1test4/test4.c

verilog/dv/caravel/hs32_soc/core1test4/test4_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test4/test1_tb.v b/verilog/dv/caravel/hs32_soc/core1test4/test4_tb.v
similarity index 84%
rename from verilog/dv/caravel/hs32_soc/core1test4/test1_tb.v
rename to verilog/dv/caravel/hs32_soc/core1test4/test4_tb.v
index 433d28e..0101ab0 100644
--- a/verilog/dv/caravel/hs32_soc/core1test4/test1_tb.v
+++ b/verilog/dv/caravel/hs32_soc/core1test4/test4_tb.v
@@ -8,13 +8,15 @@
 `include "spiflash.v"
 
 module tb();
+	parameter TEST_ID = 4;
+
 	reg clock;
-  reg RSTB;
+  	reg RSTB;
 	reg power1, power2;
 	reg power3, power4;
 
-  wire gpio;
-  wire [37:0] mprj_io;
+  	wire gpio;
+  	wire [37:0] mprj_io;
 	wire [7:0] mprj_io_0;
 
 	assign mprj_io_0 = mprj_io[7:0];
@@ -65,12 +67,16 @@
 	end
 
 	initial begin
-	    // Some weak test cases
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[0] == 16'hCAFE);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[1] == 16'h5);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[2] == 16'hCAFE);
-	    $display("Test 1 [MOV, LDR, STR Variant 1] Passed Weak Cases");
-	    //$finish;
+	    // Test cases go here
+	end
+
+	always @(*) begin
+		if(tb.uut.mprj.core1.core.EXEC.fault) begin
+			$display("%c[1;31m",27);
+			$display("Test %d: Faulted!", TEST_ID);
+			$display("%c[0m",27);
+			$finish;
+		end
 	end
 
 	always @(mprj_io) begin
@@ -114,7 +120,7 @@
 	);
 
 	spiflash #(
-		.FILENAME("test1.hex")
+		.FILENAME("test4.hex")
 	) spiflash (
 		.csb(flash_csb),
 		.clk(flash_clk),

verilog/dv/caravel/hs32_soc/core1test5/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test5/Makefile b/verilog/dv/caravel/hs32_soc/core1test5/Makefile
index 245b54a..a635e2a 100644
--- a/verilog/dv/caravel/hs32_soc/core1test5/Makefile
+++ b/verilog/dv/caravel/hs32_soc/core1test5/Makefile
@@ -9,7 +9,7 @@
 
 .SUFFIXES:
 
-PATTERN = test1
+PATTERN = test5
 
 all:  ${PATTERN:=.vcd}
 
@@ -37,6 +37,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.idx
 
 .PHONY: clean hex all

verilog/dv/caravel/hs32_soc/core1test5/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test5/README.md b/verilog/dv/caravel/hs32_soc/core1test5/README.md
index 32024b6..6621deb 100644
--- a/verilog/dv/caravel/hs32_soc/core1test5/README.md
+++ b/verilog/dv/caravel/hs32_soc/core1test5/README.md
@@ -1,6 +1,6 @@
-# HS32 Example Instruction 4
+# HS32 Example Instruction 5
 
-**LDR and STR Variant 000**
+**Interrupts and AICT**
 
 The HS32 instruction format looks like this:
 
@@ -19,48 +19,40 @@
 ## Assembly
 
 ```assembly
-MOV   R0 <-- 0x000F
-MOV   R1 <-- 0x00F0
-MOV   R2 <-- 0x0F00
-MOV   R3 <-- 0xF000
-MOV   R4 <-- 0x0BAD
-MOV   R5 <-- 0x0B09
+MOV   R0, 0xFF00
+LDR   R1, R0
 
-STR   R0, R4            ; [R4] <-- R0
-LDR   R6, R4            ; R6 <-- [R4]
+MOV   R2, high(COND1)   ; 0x5000
+MOV   R2, R2, 16        ; R2 <- (R2 << 16)
+STR   R2, R0, 01        ; STR     [Rm + imm] <- Rd
 
-STR   R2, R5, R1        ; [R5 + (R1 << 2)] <- R2
-LDR   R7, R5, R1        ; R7 <- [R5 + (R1 << 2)]
+LDR   R3, R0, 0x0010
 
-BR    0
+INT
 ```
 
 ## Hexadecimal
 
 ```hex
-0x 24 00 00 0F
-0x 24 10 00 F0
-0x 24 20 0F 00
-0x 24 30 F0 00
-0x 24 40 0B AD
-0x 24 50 0B 09
+0x 24 00 FF 00
+0x 10 10 00 00
 
-0x 30 04 00 00
-0x 10 64 00 00
+0x 24 20 50 00
+0x 20 20 28 00
+0x 34 20 00 10
 
-0x 31 25 11 00
-0x 11 75 11 00
+0x 14 30 00 10
 
-0x 50 00 00 00
+0x 90 00 00 10
 ```
 
 ## Expected result
 
-- [x] `R0   = 0x000F`
-- [x] `R1   = 0x00F0`
-- [x] `R2   = 0x0F00`
-- [x] `R3   = 0xF000`
-- [x] `R4   = 0x0BAD`
-- [x] `R5   = 0x0B09`
-- [x] `R6   = 0x000F`
-- [ ] `R7   = 0x0F00`
+- [ ] `R0   = 0x`
+- [ ] `R1   = 0x`
+- [ ] `R2   = 0x`
+- [ ] `R3   = 0x`
+- [ ] `R4   = 0x`
+- [ ] `R5   = 0x`
+- [ ] `R6   = 0x`
+- [ ] `R7   = 0x`

verilog/dv/caravel/hs32_soc/core1test5/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test5/tb.gtkw b/verilog/dv/caravel/hs32_soc/core1test5/tb.gtkw
index 361d82b..cd40e11 100644
--- a/verilog/dv/caravel/hs32_soc/core1test5/tb.gtkw
+++ b/verilog/dv/caravel/hs32_soc/core1test5/tb.gtkw
@@ -14,8 +14,8 @@
 [treeopen] tb.uut.
 [treeopen] tb.uut.mprj.
 [treeopen] tb.uut.mprj.core1.
-[treeopen] tb.uut.mprj.core1.core1.
-[treeopen] tb.uut.mprj.core1.core1.EXEC.
+[treeopen] tb.uut.mprj.core1.core.
+[treeopen] tb.uut.mprj.core1.core.EXEC.
 [treeopen] tb.uut.mprj.sram0.
 [sst_width] 265
 [signals_width] 269
@@ -51,14 +51,14 @@
 @c00200
 -PQ
 @22
-tb.uut.mprj.core1.core1.FETCH.\fifo[0][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[1][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[2][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[3][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[4][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[5][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[6][31:0]
-tb.uut.mprj.core1.core1.FETCH.\fifo[7][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[0][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[1][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[2][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[3][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[4][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[5][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[6][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[7][31:0]
 @1401200
 -PQ
 @800200
@@ -104,198 +104,198 @@
 @c00200
 -Decode
 @28
-tb.uut.mprj.core1.core1.DECODE.clk
-tb.uut.mprj.core1.core1.DECODE.reset
+tb.uut.mprj.core1.core.DECODE.clk
+tb.uut.mprj.core1.core.DECODE.reset
 @22
-tb.uut.mprj.core1.core1.DECODE.int_line[23:0]
+tb.uut.mprj.core1.core.DECODE.int_line[23:0]
 @28
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.reqd
+tb.uut.mprj.core1.core.DECODE.reqd
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.rdyd
+tb.uut.mprj.core1.core.DECODE.rdyd
 @200
 -
 @28
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.reqe
+tb.uut.mprj.core1.core.DECODE.reqe
 [color] 3
-tb.uut.mprj.core1.core1.DECODE.rdye
-tb.uut.mprj.core1.core1.DECODE.full
+tb.uut.mprj.core1.core.DECODE.rdye
+tb.uut.mprj.core1.core.DECODE.full
 @200
 -
 @22
-tb.uut.mprj.core1.core1.DECODE.instd[31:0]
+tb.uut.mprj.core1.core.DECODE.instd[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.DECODE.aluop[3:0]
+tb.uut.mprj.core1.core.DECODE.aluop[3:0]
 @28
-tb.uut.mprj.core1.core1.DECODE.bank[1:0]
+tb.uut.mprj.core1.core.DECODE.bank[1:0]
 @22
-tb.uut.mprj.core1.core1.DECODE.ctlsig[15:0]
-tb.uut.mprj.core1.core1.DECODE.imm[15:0]
-tb.uut.mprj.core1.core1.DECODE.rd[3:0]
-tb.uut.mprj.core1.core1.DECODE.rm[3:0]
-tb.uut.mprj.core1.core1.DECODE.rn[3:0]
-tb.uut.mprj.core1.core1.DECODE.shift[4:0]
+tb.uut.mprj.core1.core.DECODE.ctlsig[15:0]
+tb.uut.mprj.core1.core.DECODE.imm[15:0]
+tb.uut.mprj.core1.core.DECODE.rd[3:0]
+tb.uut.mprj.core1.core.DECODE.rm[3:0]
+tb.uut.mprj.core1.core.DECODE.rn[3:0]
+tb.uut.mprj.core1.core.DECODE.shift[4:0]
 @1401200
 -Decode
 @c00200
 -Execute
 @28
-tb.uut.mprj.core1.core1.EXEC.clk
+tb.uut.mprj.core1.core.EXEC.clk
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.req
+tb.uut.mprj.core1.core.EXEC.req
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.rdy
+tb.uut.mprj.core1.core.EXEC.rdy
 @22
-tb.uut.mprj.core1.core1.EXEC.state[3:0]
+tb.uut.mprj.core1.core.EXEC.state[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.fault
-tb.uut.mprj.core1.core1.EXEC.int_inval
+tb.uut.mprj.core1.core.EXEC.fault
+tb.uut.mprj.core1.core.EXEC.int_inval
 @c00200
 -Module I/O
 @28
-tb.uut.mprj.core1.core1.EXEC.flush
+tb.uut.mprj.core1.core.EXEC.flush
 @22
-tb.uut.mprj.core1.core1.EXEC.newpc[31:0]
+tb.uut.mprj.core1.core.EXEC.newpc[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.aluop[3:0]
-tb.uut.mprj.core1.core1.EXEC.shift[4:0]
-tb.uut.mprj.core1.core1.EXEC.imm[15:0]
-tb.uut.mprj.core1.core1.EXEC.rd[3:0]
-tb.uut.mprj.core1.core1.EXEC.rm[3:0]
-tb.uut.mprj.core1.core1.EXEC.rn[3:0]
+tb.uut.mprj.core1.core.EXEC.aluop[3:0]
+tb.uut.mprj.core1.core.EXEC.shift[4:0]
+tb.uut.mprj.core1.core.EXEC.imm[15:0]
+tb.uut.mprj.core1.core.EXEC.rd[3:0]
+tb.uut.mprj.core1.core.EXEC.rm[3:0]
+tb.uut.mprj.core1.core.EXEC.rn[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.ctlsig[15:0]
-tb.uut.mprj.core1.core1.EXEC.bank[1:0]
+tb.uut.mprj.core1.core.EXEC.ctlsig[15:0]
+tb.uut.mprj.core1.core.EXEC.bank[1:0]
 @200
 -
 @28
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.stbm
+tb.uut.mprj.core1.core.EXEC.stbm
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.ackm
+tb.uut.mprj.core1.core.EXEC.ackm
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.stlm
+tb.uut.mprj.core1.core.EXEC.stlm
 @22
-tb.uut.mprj.core1.core1.EXEC.addr[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtwm[31:0]
+tb.uut.mprj.core1.core.EXEC.addr[31:0]
+tb.uut.mprj.core1.core.EXEC.dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtwm[31:0]
 @28
 [color] 3
-tb.uut.mprj.core1.core1.EXEC.rw_mem
+tb.uut.mprj.core1.core.EXEC.rw_mem
 @200
 -
 @28
-tb.uut.mprj.core1.core1.EXEC.intrq
+tb.uut.mprj.core1.core.EXEC.intrq
 @1401200
 -Module I/O
 @c00200
 -Internal Bus
 @22
-tb.uut.mprj.core1.core1.EXEC.ibus1[31:0]
-tb.uut.mprj.core1.core1.EXEC.ibus2[31:0]
-tb.uut.mprj.core1.core1.EXEC.obus[31:0]
-tb.uut.mprj.core1.core1.EXEC.aluout[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus1[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus2[31:0]
+tb.uut.mprj.core1.core.EXEC.obus[31:0]
+tb.uut.mprj.core1.core.EXEC.aluout[31:0]
 @1401200
 -Internal Bus
 @c00200
 -ALU
 @22
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv[3:0]
+tb.uut.mprj.core1.core.EXEC.alu_nzcv[3:0]
 @28
-tb.uut.mprj.core1.core1.EXEC.alu_nzcv_out[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.carry
+tb.uut.mprj.core1.core.EXEC.alu_nzcv_out[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.carry
 @22
-tb.uut.mprj.core1.core1.EXEC.alu.i_a[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_b[31:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.i_op[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_fl[3:0]
-tb.uut.mprj.core1.core1.EXEC.alu.o_r[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_a[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_b[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_op[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_r[31:0]
 @1401200
 -ALU
 @c00200
 -Special Registers
 @22
-tb.uut.mprj.core1.core1.EXEC.r_dtrm[31:0]
-tb.uut.mprj.core1.core1.EXEC.dtw[31:0]
-tb.uut.mprj.core1.core1.EXEC.mar[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.pc_u[31:0]
-tb.uut.mprj.core1.core1.EXEC.lr_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.sp_i[31:0]
-tb.uut.mprj.core1.core1.EXEC.mcr_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.flags[31:0]
+tb.uut.mprj.core1.core.EXEC.r_dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtw[31:0]
+tb.uut.mprj.core1.core.EXEC.mar[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_s[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_u[31:0]
+tb.uut.mprj.core1.core.EXEC.lr_i[31:0]
+tb.uut.mprj.core1.core.EXEC.sp_i[31:0]
+tb.uut.mprj.core1.core.EXEC.mcr_s[31:0]
+tb.uut.mprj.core1.core.EXEC.flags[31:0]
 @1401200
 -Special Registers
 @c00200
 -Register Control
 @28
-tb.uut.mprj.core1.core1.EXEC.reg_we
-tb.uut.mprj.core1.core1.EXEC.reg_we_s
-tb.uut.mprj.core1.core1.EXEC.reg_we_u
+tb.uut.mprj.core1.core.EXEC.reg_we
+tb.uut.mprj.core1.core.EXEC.reg_we_s
+tb.uut.mprj.core1.core.EXEC.reg_we_u
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.regadra[3:0]
-tb.uut.mprj.core1.core1.EXEC.regouta[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regouta_u[31:0]
+tb.uut.mprj.core1.core.EXEC.regadra[3:0]
+tb.uut.mprj.core1.core.EXEC.regouta[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_u[31:0]
 @200
 -
 @22
-tb.uut.mprj.core1.core1.EXEC.regadrb[3:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_s[31:0]
-tb.uut.mprj.core1.core1.EXEC.regoutb_u[31:0]
+tb.uut.mprj.core1.core.EXEC.regadrb[3:0]
+tb.uut.mprj.core1.core.EXEC.regoutb[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_u[31:0]
 @1401200
 -Register Control
 @c00200
 -Supervisor Regfile
 @22
-tb.uut.mprj.core1.core1.EXEC.regfile_s.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_s.\regs[15][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[15][31:0]
 @1401200
 -Supervisor Regfile
 @c00200
 -User Regfile
 @22
-tb.uut.mprj.core1.core1.EXEC.regfile_u.wadr[3:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[0][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[1][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[2][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[3][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[4][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[5][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[6][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[7][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[8][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[9][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[10][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[11][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[12][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[13][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[14][31:0]
-tb.uut.mprj.core1.core1.EXEC.regfile_u.\regs[15][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[15][31:0]
 @1401200
 -User Regfile
 -Execute

verilog/dv/caravel/hs32_soc/core1test5/test1_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test5/test1_tb.v b/verilog/dv/caravel/hs32_soc/core1test5/test1_tb.v
deleted file mode 100644
index 433d28e..0000000
--- a/verilog/dv/caravel/hs32_soc/core1test5/test1_tb.v
+++ /dev/null
@@ -1,127 +0,0 @@
-`define DBG1
-
-`default_nettype none
-
-`timescale 1 ns / 1 ns
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module tb();
-	reg clock;
-  reg RSTB;
-	reg power1, power2;
-	reg power3, power4;
-
-  wire gpio;
-  wire [37:0] mprj_io;
-	wire [7:0] mprj_io_0;
-
-	assign mprj_io_0 = mprj_io[7:0];
-
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #12 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin
-		$dumpfile("tb.vcd");
-		$dumpvars(0, tb);
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (25) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
-		//$display("%c[1;31m",27);
-		//$display("Test 1: Failed (timed out)!");
-		//$display("%c[0m",27);
-		$finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		#2000;
-		RSTB <= 1'b1;	    // Release reset
-	end
-
-	initial begin			// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		power3 <= 1'b0;
-		power4 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-		#200;
-		power3 <= 1'b1;
-		#200;
-		power4 <= 1'b1;
-	end
-
-	initial begin
-	    // Some weak test cases
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[0] == 16'hCAFE);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[1] == 16'h5);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[2] == 16'hCAFE);
-	    $display("Test 1 [MOV, LDR, STR Variant 1] Passed Weak Cases");
-	    //$finish;
-	end
-
-	always @(mprj_io) begin
-		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
-	end
-
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-
-	wire VDD3V3 = power1;
-	wire VDD1V8 = power2;
-	wire USER_VDD3V3 = power3;
-	wire USER_VDD1V8 = power4;
-	wire VSS = 1'b0;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (USER_VDD3V3),
-		.vdda2    (USER_VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (USER_VDD1V8),
-		.vccd2	  (USER_VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-        .mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("test1.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-endmodule
-`default_nettype wire

verilog/dv/caravel/hs32_soc/core1test5/test5.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test5/test1.c b/verilog/dv/caravel/hs32_soc/core1test5/test5.c
similarity index 63%
rename from verilog/dv/caravel/hs32_soc/core1test5/test1.c
rename to verilog/dv/caravel/hs32_soc/core1test5/test5.c
index c8db3ad..184fc9f 100644
--- a/verilog/dv/caravel/hs32_soc/core1test5/test1.c
+++ b/verilog/dv/caravel/hs32_soc/core1test5/test5.c
@@ -13,17 +13,13 @@
 	reg_la0_data = 0b00; // [0] is low means stop reset
 
 	// Write
-  ((volatile uint32_t*) 0x30000000)[0] = 0x2400000F;
-  ((volatile uint32_t*) 0x30000000)[1] = 0x241000F0;
-  ((volatile uint32_t*) 0x30000000)[2] = 0x24200F00;
-  ((volatile uint32_t*) 0x30000000)[3] = 0x2430F000;
-  ((volatile uint32_t*) 0x30000000)[4] = 0x24400BAD;
-  ((volatile uint32_t*) 0x30000000)[5] = 0x24500B09;
-  ((volatile uint32_t*) 0x30000000)[6] = 0x30040000;
-  ((volatile uint32_t*) 0x30000000)[7] = 0x10640000;
-  ((volatile uint32_t*) 0x30000000)[8] = 0x31251100;
-  ((volatile uint32_t*) 0x30000000)[9] = 0x11751100;
-  ((volatile uint32_t*) 0x30000000)[10] = 0x50000000;
+  ((volatile uint32_t*) 0x30000000)[0] = 0x2400FF00;
+  ((volatile uint32_t*) 0x30000000)[1] = 0x10100000;
+  ((volatile uint32_t*) 0x30000000)[2] = 0x24205000;
+  ((volatile uint32_t*) 0x30000000)[3] = 0x20202800;
+  ((volatile uint32_t*) 0x30000000)[4] = 0x34200010;
+  ((volatile uint32_t*) 0x30000000)[5] = 0x14300010;
+  ((volatile uint32_t*) 0x30000000)[6] = 0x90000010;
 
 	// Release control and reset
 	reg_la0_data = 0b11; // [1] is high means release control back to hs32

verilog/dv/caravel/hs32_soc/core1test5/test5_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v b/verilog/dv/caravel/hs32_soc/core1test5/test5_tb.v
similarity index 85%
copy from verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v
copy to verilog/dv/caravel/hs32_soc/core1test5/test5_tb.v
index 433d28e..02e527d 100644
--- a/verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v
+++ b/verilog/dv/caravel/hs32_soc/core1test5/test5_tb.v
@@ -8,6 +8,8 @@
 `include "spiflash.v"
 
 module tb();
+	parameter TEST_ID = 5;
+
 	reg clock;
   reg RSTB;
 	reg power1, power2;
@@ -65,12 +67,16 @@
 	end
 
 	initial begin
-	    // Some weak test cases
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[0] == 16'hCAFE);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[1] == 16'h5);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[2] == 16'hCAFE);
-	    $display("Test 1 [MOV, LDR, STR Variant 1] Passed Weak Cases");
-	    //$finish;
+	    // Test cases go here
+	end
+
+	always @(*) begin
+		if(tb.uut.mprj.core1.core.EXEC.fault) begin
+			$display("%c[1;31m",27);
+			$display("Test %d: Faulted!", TEST_ID);
+			$display("%c[0m",27);
+			$finish;
+		end
 	end
 
 	always @(mprj_io) begin
@@ -114,7 +120,7 @@
 	);
 
 	spiflash #(
-		.FILENAME("test1.hex")
+		.FILENAME("test5.hex")
 	) spiflash (
 		.csb(flash_csb),
 		.clk(flash_clk),

verilog/dv/caravel/hs32_soc/core1test6/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test1.no/Makefile b/verilog/dv/caravel/hs32_soc/core1test6/Makefile
similarity index 93%
copy from verilog/dv/caravel/hs32_soc/core1test1.no/Makefile
copy to verilog/dv/caravel/hs32_soc/core1test6/Makefile
index 245b54a..5488205 100644
--- a/verilog/dv/caravel/hs32_soc/core1test1.no/Makefile
+++ b/verilog/dv/caravel/hs32_soc/core1test6/Makefile
@@ -9,7 +9,7 @@
 
 .SUFFIXES:
 
-PATTERN = test1
+PATTERN = test6
 
 all:  ${PATTERN:=.vcd}
 
@@ -37,6 +37,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.idx
 
 .PHONY: clean hex all

verilog/dv/caravel/hs32_soc/core1test6/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test6/README.md b/verilog/dv/caravel/hs32_soc/core1test6/README.md
new file mode 100644
index 0000000..8f52b27
--- /dev/null
+++ b/verilog/dv/caravel/hs32_soc/core1test6/README.md
@@ -0,0 +1,46 @@
+# HS32 Example Instruction 6
+
+**Branching Test**
+
+The HS32 instruction format looks like this:
+
+| Type   | Wire Format                               |
+| ------ | ----------------------------------------- |
+| I-Type | `oooo_oooo_dddd_mmmm iiii_iiii_iiii_iiii` |
+| R-Type | `oooo_oooo_dddd_mmmm nnnn_ssss_sDDb_bxxx` |
+
+The hexadecimal format looks like this:
+
+| Type   | bram3.hex   | bram2.hex   | bram1.hex   | bram0.hex   |
+| ------ | ----------- | ----------- | ----------- | ----------- |
+| I-Type | `oooo_oooo` | `dddd_mmmm` | `iiii_iiii` | `iiii_iiii` |
+| R-Type | `oooo_oooo` | `dddd_mmmm` | `nnnn_ssss` | `sDDb_bxxx` |
+
+## Assembly
+
+```assembly
+MOV   PC, 0x0008
+LDR   R0, PC
+```
+
+## Hexadecimal
+
+```hex
+0x 24 F0 00 00
+
+
+
+0x 50 00 00 00
+```
+
+## Expected result
+
+- [x] `R0   = 0xB412`
+- [x] `R1   = 0xB412`
+- [x] `R2   = 0x0ADD`
+- [x] `R3   = 0x0BAD`
+- [ ] `R4   = 0x0B09`
+- [ ] `R5   = 0x21660000`
+- [ ] `R6   = 0x0ADD`
+- [ ] `R6_u = 0x0ADD`
+- [ ] `R7   = 0x0ADD0000`

verilog/dv/caravel/hs32_soc/core1test6/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test6/tb.gtkw b/verilog/dv/caravel/hs32_soc/core1test6/tb.gtkw
new file mode 100644
index 0000000..bcaa546
--- /dev/null
+++ b/verilog/dv/caravel/hs32_soc/core1test6/tb.gtkw
@@ -0,0 +1,370 @@
+[*]
+[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
+[*] Fri Dec 18 19:17:22 2020
+[*]
+[dumpfile] "/data/caravel-hs32core/verilog/dv/caravel/hs32_soc/core1test6/dump.vcd"
+[dumpfile_mtime] "Fri Dec 18 18:47:04 2020"
+[dumpfile_size] 328739070
+[savefile] "/data/caravel-hs32core/verilog/dv/caravel/hs32_soc/core1test6/tb.gtkw"
+[timestart] 227809800
+[size] 1536 778
+[pos] -1 -1
+*-16.106964 227916000 230148000 228036000 227460000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] tb.
+[treeopen] tb.uut.
+[treeopen] tb.uut.mprj.
+[treeopen] tb.uut.mprj.core1.
+[treeopen] tb.uut.mprj.core1.core.
+[treeopen] tb.uut.mprj.core1.core.EXEC.
+[treeopen] tb.uut.mprj.sram0.
+[sst_width] 261
+[signals_width] 344
+[sst_expanded] 1
+[sst_vpaned_height] 223
+@800200
+-WBS
+@28
+tb.uut.mprj.wb_clk_i
+tb.uut.mprj.wb_rst_i
+tb.uut.mprj.wbs_ack_o
+@22
+tb.uut.mprj.wbs_adr_i[31:0]
+@28
+tb.uut.mprj.wbs_cyc_i
+@22
+tb.uut.mprj.wbs_dat_i[31:0]
+tb.uut.mprj.wbs_dat_o[31:0]
+tb.uut.mprj.wbs_sel_i[3:0]
+@28
+tb.uut.mprj.wbs_stb_i
+tb.uut.mprj.wbs_we_i
+@1000200
+-WBS
+@28
+tb.uut.mprj.core1.ram_ce
+tb.uut.mprj.core1.bsy
+tb.uut.mprj.sram0.csb0
+tb.uut.mprj.sram0.csb0_reg
+@22
+tb.uut.mprj.dtw_e[15:0]
+tb.uut.mprj.dtw_n[15:0]
+@c00200
+-PQ
+@22
+tb.uut.mprj.core1.core.FETCH.\fifo[0][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[1][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[2][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[3][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[4][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[5][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[6][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[7][31:0]
+@1401200
+-PQ
+@c00200
+-Fetch
+@28
+tb.uut.mprj.core1.core.FETCH.clk
+@22
+tb.uut.mprj.core1.core.FETCH.addr[31:0]
+tb.uut.mprj.core1.core.FETCH.dtr[31:0]
+@28
+tb.uut.mprj.core1.core.FETCH.ackm
+tb.uut.mprj.core1.core.FETCH.flush
+@22
+tb.uut.mprj.core1.core.FETCH.newpc[31:0]
+tb.uut.mprj.core1.core.FETCH.instd[31:0]
+@1401200
+-Fetch
+@c00200
+-BRAM CTL
+@22
+tb.uut.mprj.core1.bram_ctl.i_addr[11:0]
+@28
+tb.uut.mprj.core1.bram_ctl.i_clk
+@22
+tb.uut.mprj.core1.bram_ctl.i_dwrite[31:0]
+@28
+tb.uut.mprj.core1.bram_ctl.i_reset
+tb.uut.mprj.core1.bram_ctl.i_rw
+[color] 3
+tb.uut.mprj.core1.bram_ctl.i_stb
+[color] 3
+tb.uut.mprj.core1.bram_ctl.o_ack
+@22
+tb.uut.mprj.core1.bram_ctl.o_dread[31:0]
+@28
+tb.uut.mprj.core1.bram_ctl.r_bsy
+@200
+-
+@22
+tb.uut.mprj.core1.bram_ctl.r_dread[31:0]
+tb.uut.mprj.core1.bram_ctl.dbuf[31:0]
+tb.uut.mprj.core1.bram_ctl.wbuf[31:0]
+@200
+-
+@22
+tb.uut.mprj.core1.bram_ctl.a0[9:0]
+tb.uut.mprj.core1.bram_ctl.a1[9:0]
+tb.uut.mprj.core1.bram_ctl.a2[9:0]
+tb.uut.mprj.core1.bram_ctl.a3[9:0]
+tb.uut.mprj.core1.bram_ctl.cpu_addr_e[15:0]
+tb.uut.mprj.core1.bram_ctl.cpu_addr_n[15:0]
+tb.uut.mprj.core1.bram_ctl.dbuf0[31:0]
+tb.uut.mprj.core1.bram_ctl.dbuf1[31:0]
+tb.uut.mprj.core1.bram_ctl.dbuf2[31:0]
+tb.uut.mprj.core1.bram_ctl.dbuf3[31:0]
+@1401200
+-BRAM CTL
+@800200
+-Decode
+@28
+tb.uut.mprj.core1.core.DECODE.clk
+tb.uut.mprj.core1.core.DECODE.reset
+@22
+tb.uut.mprj.core1.core.DECODE.int_line[23:0]
+@28
+[color] 3
+tb.uut.mprj.core1.core.DECODE.reqd
+[color] 3
+tb.uut.mprj.core1.core.DECODE.rdyd
+@200
+-
+@28
+[color] 3
+tb.uut.mprj.core1.core.DECODE.reqe
+[color] 3
+tb.uut.mprj.core1.core.DECODE.rdye
+@29
+tb.uut.mprj.core1.core.DECODE.r_hasnext
+@200
+-
+@22
+tb.uut.mprj.core1.core.DECODE.instd[31:0]
+@200
+-
+@22
+tb.uut.mprj.core1.core.DECODE.aluop[3:0]
+@28
+tb.uut.mprj.core1.core.DECODE.bank[1:0]
+@22
+tb.uut.mprj.core1.core.DECODE.ctlsig[15:0]
+tb.uut.mprj.core1.core.DECODE.imm[15:0]
+tb.uut.mprj.core1.core.DECODE.rd[3:0]
+tb.uut.mprj.core1.core.DECODE.rm[3:0]
+tb.uut.mprj.core1.core.DECODE.rn[3:0]
+tb.uut.mprj.core1.core.DECODE.shift[4:0]
+@1000200
+-Decode
+@800200
+-Execute
+@28
+tb.uut.mprj.core1.core.EXEC.clk
+[color] 3
+tb.uut.mprj.core1.core.EXEC.req
+[color] 3
+tb.uut.mprj.core1.core.EXEC.rdy
+@22
+tb.uut.mprj.core1.core.EXEC.state[3:0]
+@28
+tb.uut.mprj.core1.core.EXEC.fault
+tb.uut.mprj.core1.core.EXEC.int_inval
+@22
+tb.uut.mprj.core1.core.EXEC.control[54:0]
+tb.uut.mprj.core1.core.EXEC.r_control[54:0]
+@800200
+-Module I/O
+@28
+tb.uut.mprj.core1.core.EXEC.flush
+@22
+tb.uut.mprj.core1.core.EXEC.newpc[31:0]
+@200
+-
+@22
+tb.uut.mprj.core1.core.EXEC.aluop[3:0]
+tb.uut.mprj.core1.core.EXEC.shift[4:0]
+tb.uut.mprj.core1.core.EXEC.imm[15:0]
+tb.uut.mprj.core1.core.EXEC.rd[3:0]
+tb.uut.mprj.core1.core.EXEC.rm[3:0]
+tb.uut.mprj.core1.core.EXEC.rn[3:0]
+@28
+tb.uut.mprj.core1.core.EXEC.ctlsig[15:0]
+tb.uut.mprj.core1.core.EXEC.bank[1:0]
+@200
+-
+@28
+[color] 3
+tb.uut.mprj.core1.core.EXEC.stbm
+[color] 3
+tb.uut.mprj.core1.core.EXEC.ackm
+[color] 3
+tb.uut.mprj.core1.core.EXEC.stlm
+@22
+tb.uut.mprj.core1.core.EXEC.addr[31:0]
+tb.uut.mprj.core1.core.EXEC.dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtwm[31:0]
+@28
+[color] 3
+tb.uut.mprj.core1.core.EXEC.rw_mem
+@200
+-
+@28
+tb.uut.mprj.core1.core.EXEC.intrq
+@1000200
+-Module I/O
+@c00200
+-Internal Bus
+@22
+tb.uut.mprj.core1.core.EXEC.ibus1[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus2[31:0]
+tb.uut.mprj.core1.core.EXEC.obus[31:0]
+tb.uut.mprj.core1.core.EXEC.aluout[31:0]
+@1401200
+-Internal Bus
+@800200
+-ALU
+@22
+tb.uut.mprj.core1.core.EXEC.alu_nzcv[3:0]
+@28
+tb.uut.mprj.core1.core.EXEC.alu_nzcv_out[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.carry
+@22
+tb.uut.mprj.core1.core.EXEC.alu.i_a[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_b[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_op[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_r[31:0]
+@1000200
+-ALU
+@800200
+-Special Registers
+@22
+tb.uut.mprj.core1.core.EXEC.r_dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtw[31:0]
+tb.uut.mprj.core1.core.EXEC.mar[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_s[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_u[31:0]
+tb.uut.mprj.core1.core.EXEC.lr_i[31:0]
+tb.uut.mprj.core1.core.EXEC.sp_i[31:0]
+tb.uut.mprj.core1.core.EXEC.mcr_s[31:0]
+@28
+tb.uut.mprj.core1.core.EXEC.flags[31:0]
+@1000200
+-Special Registers
+@c00200
+-Register Control
+@28
+tb.uut.mprj.core1.core.EXEC.reg_we
+tb.uut.mprj.core1.core.EXEC.reg_we_s
+tb.uut.mprj.core1.core.EXEC.reg_we_u
+@200
+-
+@22
+tb.uut.mprj.core1.core.EXEC.regadra[3:0]
+tb.uut.mprj.core1.core.EXEC.regouta[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_u[31:0]
+@200
+-
+@22
+tb.uut.mprj.core1.core.EXEC.regadrb[3:0]
+tb.uut.mprj.core1.core.EXEC.regoutb[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_u[31:0]
+@1401200
+-Register Control
+@c00200
+-Supervisor Regfile
+@22
+tb.uut.mprj.core1.core.EXEC.regfile_s.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[15][31:0]
+@1401200
+-Supervisor Regfile
+@c00200
+-User Regfile
+@22
+tb.uut.mprj.core1.core.EXEC.regfile_u.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[15][31:0]
+@1401200
+-User Regfile
+@1000200
+-Execute
+@c00200
+-sram0
+@22
+tb.uut.mprj.sram0.addr0[7:0]
+@28
+tb.uut.mprj.sram0.clk0
+tb.uut.mprj.sram0.csb0
+@22
+tb.uut.mprj.sram0.din0[31:0]
+tb.uut.mprj.sram0.dout0[31:0]
+@28
+tb.uut.mprj.sram0.web0
+tb.uut.mprj.sram0.wmask0[3:0]
+@1401200
+-sram0
+@c00200
+-sram1
+@22
+tb.uut.mprj.sram1.addr0[7:0]
+@28
+tb.uut.mprj.sram1.clk0
+tb.uut.mprj.sram1.csb0
+@22
+tb.uut.mprj.sram1.din0[31:0]
+tb.uut.mprj.sram1.dout0[31:0]
+@28
+tb.uut.mprj.sram1.web0
+@22
+tb.uut.mprj.sram1.wmask0[3:0]
+@1401200
+-sram1
+@c00200
+-sram3
+@22
+tb.uut.mprj.sram2.addr0[7:0]
+@28
+tb.uut.mprj.sram2.clk0
+tb.uut.mprj.sram2.csb0
+@22
+tb.uut.mprj.sram2.din0[31:0]
+tb.uut.mprj.sram2.dout0[31:0]
+@28
+tb.uut.mprj.sram2.web0
+tb.uut.mprj.sram2.wmask0[3:0]
+@1401200
+-sram3
+[pattern_trace] 1
+[pattern_trace] 0

verilog/dv/caravel/hs32_soc/core1test6/test6.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test6/test6.c b/verilog/dv/caravel/hs32_soc/core1test6/test6.c
new file mode 100644
index 0000000..3912a79
--- /dev/null
+++ b/verilog/dv/caravel/hs32_soc/core1test6/test6.c
@@ -0,0 +1,37 @@
+#include "../../defs.h"
+
+void main()
+{
+	// Reset
+	reg_la0_ena = 0x00000000;    // [31:0]
+	reg_la1_ena = 0xFFFFFFFF;    // [63:32]
+	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
+	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
+	
+	// Reset and control bus
+	reg_la0_data = 0b01; // [0] is high means reset
+	reg_la0_data = 0b00; // [0] is low means stop reset
+
+	// Write
+  ((volatile uint32_t*) 0x30000000)[0] = 0x24F00000;
+  ((volatile uint32_t*) 0x30000000)[1] = 0x50000000;
+
+	// Release control and reset
+	reg_la0_data = 0b11; // [1] is high means release control back to hs32
+	reg_la0_data = 0b10;
+
+	// Configure lower 8-IOs as user output
+	// Observe counter value in the testbench
+	reg_mprj_io_0 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_1 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_2 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_3 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_4 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_5 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_6 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_7 =  GPIO_MODE_USER_STD_OUTPUT;
+
+  // Apply configuration
+  reg_mprj_xfer = 1;
+  while (reg_mprj_xfer == 1);
+}

verilog/dv/caravel/hs32_soc/core1test6/test6_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v b/verilog/dv/caravel/hs32_soc/core1test6/test6_tb.v
similarity index 82%
copy from verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v
copy to verilog/dv/caravel/hs32_soc/core1test6/test6_tb.v
index 433d28e..05b86f2 100644
--- a/verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v
+++ b/verilog/dv/caravel/hs32_soc/core1test6/test6_tb.v
@@ -8,13 +8,15 @@
 `include "spiflash.v"
 
 module tb();
+	parameter TEST_ID = 6;
+
 	reg clock;
-  reg RSTB;
+  	reg RSTB;
 	reg power1, power2;
 	reg power3, power4;
 
-  wire gpio;
-  wire [37:0] mprj_io;
+  	wire gpio;
+  	wire [37:0] mprj_io;
 	wire [7:0] mprj_io_0;
 
 	assign mprj_io_0 = mprj_io[7:0];
@@ -65,12 +67,16 @@
 	end
 
 	initial begin
-	    // Some weak test cases
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[0] == 16'hCAFE);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[1] == 16'h5);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[2] == 16'hCAFE);
-	    $display("Test 1 [MOV, LDR, STR Variant 1] Passed Weak Cases");
-	    //$finish;
+	    // Test cases go here
+	end
+
+	always @(*) begin
+		if(tb.uut.mprj.core1.core.EXEC.fault) begin
+			$display("%c[1;31m",27);
+			$display("Test %d: Faulted!", TEST_ID);
+			$display("%c[0m",27);
+			$finish;
+		end
 	end
 
 	always @(mprj_io) begin
@@ -105,7 +111,7 @@
 		.vssd2	  (VSS),
 		.clock	  (clock),
 		.gpio     (gpio),
-        .mprj_io  (mprj_io),
+    .mprj_io  (mprj_io),
 		.flash_csb(flash_csb),
 		.flash_clk(flash_clk),
 		.flash_io0(flash_io0),
@@ -114,7 +120,7 @@
 	);
 
 	spiflash #(
-		.FILENAME("test1.hex")
+		.FILENAME("test6.hex")
 	) spiflash (
 		.csb(flash_csb),
 		.clk(flash_clk),

verilog/dv/caravel/hs32_soc/core1test7/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test1.no/Makefile b/verilog/dv/caravel/hs32_soc/core1test7/Makefile
similarity index 93%
rename from verilog/dv/caravel/hs32_soc/core1test1.no/Makefile
rename to verilog/dv/caravel/hs32_soc/core1test7/Makefile
index 245b54a..49aa8c1 100644
--- a/verilog/dv/caravel/hs32_soc/core1test1.no/Makefile
+++ b/verilog/dv/caravel/hs32_soc/core1test7/Makefile
@@ -9,7 +9,7 @@
 
 .SUFFIXES:
 
-PATTERN = test1
+PATTERN = test7
 
 all:  ${PATTERN:=.vcd}
 
@@ -37,6 +37,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.idx
 
 .PHONY: clean hex all

verilog/dv/caravel/hs32_soc/core1test7/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test7/README.md b/verilog/dv/caravel/hs32_soc/core1test7/README.md
new file mode 100644
index 0000000..21f94d2
--- /dev/null
+++ b/verilog/dv/caravel/hs32_soc/core1test7/README.md
@@ -0,0 +1,64 @@
+# HS32 Example Instruction 5
+
+**Interrupts and AICT**
+
+The HS32 instruction format looks like this:
+
+| Type   | Wire Format                               |
+| ------ | ----------------------------------------- |
+| I-Type | `oooo_oooo_dddd_mmmm iiii_iiii_iiii_iiii` |
+| R-Type | `oooo_oooo_dddd_mmmm nnnn_ssss_sDDb_bxxx` |
+
+The hexadecimal format looks like this:
+
+| Type   | bram3.hex   | bram2.hex   | bram1.hex   | bram0.hex   |
+| ------ | ----------- | ----------- | ----------- | ----------- |
+| I-Type | `oooo_oooo` | `dddd_mmmm` | `iiii_iiii` | `iiii_iiii` |
+| R-Type | `oooo_oooo` | `dddd_mmmm` | `nnnn_ssss` | `sDDb_bxxx` |
+
+## Assembly
+
+```assembly
+MOV   R0, 0xFF00
+LDR   R1, R0
+
+MOV   R2, 0x0BA0
+MOV   R3, high(COND1)   ; 0x5000
+MOV   R3, R3, 16        ; R3 <- (R3 << 16)
+STR   R3, R2            ; [R2] <-- R3
+MOV   R4, 0x0BA1
+STR   R4, R0, 0x0010    ; STR     [Rm + imm] <- Rd
+
+LDR   R5, R0, 0x0010
+
+INT   0x0003
+```
+
+## Hexadecimal
+
+```hex
+0x 24 00 FF 00
+0x 10 10 00 00
+
+0x 24 20 0B A0
+0x 24 30 50 00
+0x 20 30 38 00
+0x 30 23 00 00
+0x 24 40 0B A1
+0x 34 40 00 10
+
+0x 14 50 00 10
+
+0x 90 00 00 03
+```
+
+## Expected result
+
+- [ ] `R0   = 0x`
+- [ ] `R1   = 0x`
+- [ ] `R2   = 0x`
+- [ ] `R3   = 0x`
+- [ ] `R4   = 0x`
+- [ ] `R5   = 0x`
+- [ ] `R6   = 0x`
+- [ ] `R7   = 0x`

verilog/dv/caravel/hs32_soc/core1test7/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test7/tb.gtkw b/verilog/dv/caravel/hs32_soc/core1test7/tb.gtkw
new file mode 100644
index 0000000..831f9e2
--- /dev/null
+++ b/verilog/dv/caravel/hs32_soc/core1test7/tb.gtkw
@@ -0,0 +1,369 @@
+[*]
+[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
+[*] Sat Dec 19 06:57:44 2020
+[*]
+[dumpfile] "/data/caravel-hs32core/verilog/dv/caravel/hs32_soc/core1test7/dump.vcd"
+[dumpfile_mtime] "Sat Dec 19 06:49:49 2020"
+[dumpfile_size] 309579312
+[savefile] "/data/caravel-hs32core/verilog/dv/caravel/hs32_soc/core1test7/tb.gtkw"
+[timestart] 160515500
+[size] 1536 801
+[pos] -9 -33
+*-16.106964 160668000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] tb.
+[treeopen] tb.uut.
+[treeopen] tb.uut.mprj.
+[treeopen] tb.uut.mprj.core1.
+[treeopen] tb.uut.mprj.core1.core.
+[treeopen] tb.uut.mprj.core1.core.EXEC.
+[treeopen] tb.uut.mprj.sram0.
+[sst_width] 265
+[signals_width] 269
+[sst_expanded] 1
+[sst_vpaned_height] 222
+@c00200
+-WBS
+@28
+tb.uut.mprj.wb_clk_i
+tb.uut.mprj.wb_rst_i
+tb.uut.mprj.wbs_ack_o
+@22
+tb.uut.mprj.wbs_adr_i[31:0]
+@28
+tb.uut.mprj.wbs_cyc_i
+@22
+tb.uut.mprj.wbs_dat_i[31:0]
+tb.uut.mprj.wbs_dat_o[31:0]
+tb.uut.mprj.wbs_sel_i[3:0]
+@28
+tb.uut.mprj.wbs_stb_i
+tb.uut.mprj.wbs_we_i
+@1401200
+-WBS
+@28
+tb.uut.mprj.core1.mmio_conn.clk
+tb.uut.mprj.core1.mmio_conn.in_aict
+tb.uut.mprj.core1.mmio_conn.none
+@22
+tb.uut.mprj.core1.mmio_conn.aict_base[31:0]
+@28
+tb.uut.mprj.core1.mmio_conn.o_ack
+@22
+tb.uut.mprj.core1.mmio_conn.o_stb[3:0]
+tb.uut.mprj.core1.mmio_conn.i_addr[31:0]
+tb.uut.mprj.core1.mmio_conn.i_ack[3:0]
+@23
+tb.uut.mprj.core1.mmio_conn.sel[3:0]
+@200
+-
+@c00200
+-SRAM
+@28
+tb.uut.mprj.core1.ram_ce
+tb.uut.mprj.core1.bsy
+tb.uut.mprj.sram0.csb0
+tb.uut.mprj.sram0.csb0_reg
+@22
+tb.uut.mprj.dtw_e[15:0]
+tb.uut.mprj.dtw_n[15:0]
+@1401200
+-SRAM
+@c00200
+-PQ
+@22
+tb.uut.mprj.core1.core.FETCH.\fifo[0][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[1][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[2][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[3][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[4][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[5][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[6][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[7][31:0]
+@1401200
+-PQ
+@c00200
+-BRAM CTL
+@22
+tb.uut.mprj.core1.bram_ctl.i_addr[11:0]
+@28
+tb.uut.mprj.core1.bram_ctl.i_clk
+@22
+tb.uut.mprj.core1.bram_ctl.i_dwrite[31:0]
+@28
+tb.uut.mprj.core1.bram_ctl.i_reset
+tb.uut.mprj.core1.bram_ctl.i_rw
+[color] 3
+tb.uut.mprj.core1.bram_ctl.i_stb
+[color] 3
+tb.uut.mprj.core1.bram_ctl.o_ack
+@22
+tb.uut.mprj.core1.bram_ctl.o_dread[31:0]
+@28
+tb.uut.mprj.core1.bram_ctl.r_bsy
+@200
+-
+@22
+tb.uut.mprj.core1.bram_ctl.r_dread[31:0]
+tb.uut.mprj.core1.bram_ctl.dbuf[31:0]
+tb.uut.mprj.core1.bram_ctl.wbuf[31:0]
+@200
+-
+@22
+tb.uut.mprj.core1.bram_ctl.a0[9:0]
+tb.uut.mprj.core1.bram_ctl.a1[9:0]
+tb.uut.mprj.core1.bram_ctl.a2[9:0]
+tb.uut.mprj.core1.bram_ctl.a3[9:0]
+tb.uut.mprj.core1.bram_ctl.cpu_addr_e[15:0]
+tb.uut.mprj.core1.bram_ctl.cpu_addr_n[15:0]
+tb.uut.mprj.core1.bram_ctl.dbuf0[31:0]
+tb.uut.mprj.core1.bram_ctl.dbuf1[31:0]
+tb.uut.mprj.core1.bram_ctl.dbuf2[31:0]
+tb.uut.mprj.core1.bram_ctl.dbuf3[31:0]
+@1401200
+-BRAM CTL
+@c00200
+-Decode
+@28
+tb.uut.mprj.core1.core.DECODE.clk
+tb.uut.mprj.core1.core.DECODE.reset
+@22
+tb.uut.mprj.core1.core.DECODE.int_line[23:0]
+@28
+[color] 3
+tb.uut.mprj.core1.core.DECODE.reqd
+[color] 3
+tb.uut.mprj.core1.core.DECODE.rdyd
+@200
+-
+@28
+[color] 3
+tb.uut.mprj.core1.core.DECODE.reqe
+[color] 3
+tb.uut.mprj.core1.core.DECODE.rdye
+@200
+-
+@22
+tb.uut.mprj.core1.core.DECODE.instd[31:0]
+@200
+-
+@22
+tb.uut.mprj.core1.core.DECODE.aluop[3:0]
+@28
+tb.uut.mprj.core1.core.DECODE.bank[1:0]
+@22
+tb.uut.mprj.core1.core.DECODE.ctlsig[15:0]
+tb.uut.mprj.core1.core.DECODE.imm[15:0]
+tb.uut.mprj.core1.core.DECODE.rd[3:0]
+tb.uut.mprj.core1.core.DECODE.rm[3:0]
+tb.uut.mprj.core1.core.DECODE.rn[3:0]
+tb.uut.mprj.core1.core.DECODE.shift[4:0]
+@1401200
+-Decode
+@800200
+-Execute
+@28
+tb.uut.mprj.core1.core.EXEC.clk
+[color] 3
+tb.uut.mprj.core1.core.EXEC.req
+[color] 3
+tb.uut.mprj.core1.core.EXEC.rdy
+@22
+tb.uut.mprj.core1.core.EXEC.state[3:0]
+@28
+tb.uut.mprj.core1.core.EXEC.fault
+tb.uut.mprj.core1.core.EXEC.int_inval
+@800200
+-Module I/O
+@28
+tb.uut.mprj.core1.core.EXEC.flush
+@22
+tb.uut.mprj.core1.core.EXEC.newpc[31:0]
+@200
+-
+@22
+tb.uut.mprj.core1.core.EXEC.aluop[3:0]
+tb.uut.mprj.core1.core.EXEC.shift[4:0]
+tb.uut.mprj.core1.core.EXEC.imm[15:0]
+tb.uut.mprj.core1.core.EXEC.rd[3:0]
+tb.uut.mprj.core1.core.EXEC.rm[3:0]
+tb.uut.mprj.core1.core.EXEC.rn[3:0]
+@28
+tb.uut.mprj.core1.core.EXEC.ctlsig[15:0]
+tb.uut.mprj.core1.core.EXEC.bank[1:0]
+@200
+-
+@28
+[color] 3
+tb.uut.mprj.core1.core.EXEC.stbm
+[color] 3
+tb.uut.mprj.core1.core.EXEC.ackm
+[color] 3
+tb.uut.mprj.core1.core.EXEC.stlm
+@22
+tb.uut.mprj.core1.core.EXEC.addr[31:0]
+tb.uut.mprj.core1.core.EXEC.dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtwm[31:0]
+@28
+[color] 3
+tb.uut.mprj.core1.core.EXEC.rw_mem
+@200
+-
+@28
+tb.uut.mprj.core1.core.EXEC.intrq
+@1000200
+-Module I/O
+@c00200
+-Internal Bus
+@22
+tb.uut.mprj.core1.core.EXEC.ibus1[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus2[31:0]
+tb.uut.mprj.core1.core.EXEC.obus[31:0]
+tb.uut.mprj.core1.core.EXEC.aluout[31:0]
+@1401200
+-Internal Bus
+@c00200
+-ALU
+@22
+tb.uut.mprj.core1.core.EXEC.alu_nzcv[3:0]
+@28
+tb.uut.mprj.core1.core.EXEC.alu_nzcv_out[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.carry
+@22
+tb.uut.mprj.core1.core.EXEC.alu.i_a[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_b[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_op[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_r[31:0]
+@1401200
+-ALU
+@c00200
+-Special Registers
+@22
+tb.uut.mprj.core1.core.EXEC.r_dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtw[31:0]
+tb.uut.mprj.core1.core.EXEC.mar[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_s[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_u[31:0]
+tb.uut.mprj.core1.core.EXEC.lr_i[31:0]
+tb.uut.mprj.core1.core.EXEC.sp_i[31:0]
+tb.uut.mprj.core1.core.EXEC.mcr_s[31:0]
+tb.uut.mprj.core1.core.EXEC.flags[31:0]
+@1401200
+-Special Registers
+@c00200
+-Register Control
+@28
+tb.uut.mprj.core1.core.EXEC.reg_we
+tb.uut.mprj.core1.core.EXEC.reg_we_s
+tb.uut.mprj.core1.core.EXEC.reg_we_u
+@200
+-
+@22
+tb.uut.mprj.core1.core.EXEC.regadra[3:0]
+tb.uut.mprj.core1.core.EXEC.regouta[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_u[31:0]
+@200
+-
+@22
+tb.uut.mprj.core1.core.EXEC.regadrb[3:0]
+tb.uut.mprj.core1.core.EXEC.regoutb[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_u[31:0]
+@1401200
+-Register Control
+@c00200
+-Supervisor Regfile
+@22
+tb.uut.mprj.core1.core.EXEC.regfile_s.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[15][31:0]
+@1401200
+-Supervisor Regfile
+@c00200
+-User Regfile
+@22
+tb.uut.mprj.core1.core.EXEC.regfile_u.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[15][31:0]
+@1401200
+-User Regfile
+@1000200
+-Execute
+@c00200
+-sram0
+@22
+tb.uut.mprj.sram0.addr0[7:0]
+@28
+tb.uut.mprj.sram0.clk0
+tb.uut.mprj.sram0.csb0
+@22
+tb.uut.mprj.sram0.din0[31:0]
+tb.uut.mprj.sram0.dout0[31:0]
+@28
+tb.uut.mprj.sram0.web0
+tb.uut.mprj.sram0.wmask0[3:0]
+@1401200
+-sram0
+@c00200
+-sram1
+@22
+tb.uut.mprj.sram1.addr0[7:0]
+@28
+tb.uut.mprj.sram1.clk0
+tb.uut.mprj.sram1.csb0
+@22
+tb.uut.mprj.sram1.din0[31:0]
+tb.uut.mprj.sram1.dout0[31:0]
+@28
+tb.uut.mprj.sram1.web0
+@22
+tb.uut.mprj.sram1.wmask0[3:0]
+@1401200
+-sram1
+@c00200
+-sram3
+@22
+tb.uut.mprj.sram2.addr0[7:0]
+@28
+tb.uut.mprj.sram2.clk0
+tb.uut.mprj.sram2.csb0
+@22
+tb.uut.mprj.sram2.din0[31:0]
+tb.uut.mprj.sram2.dout0[31:0]
+@28
+tb.uut.mprj.sram2.web0
+tb.uut.mprj.sram2.wmask0[3:0]
+@1401200
+-sram3
+[pattern_trace] 1
+[pattern_trace] 0

verilog/dv/caravel/hs32_soc/core1test7/test7.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test5/test1.c b/verilog/dv/caravel/hs32_soc/core1test7/test7.c
similarity index 63%
copy from verilog/dv/caravel/hs32_soc/core1test5/test1.c
copy to verilog/dv/caravel/hs32_soc/core1test7/test7.c
index c8db3ad..b7158b6 100644
--- a/verilog/dv/caravel/hs32_soc/core1test5/test1.c
+++ b/verilog/dv/caravel/hs32_soc/core1test7/test7.c
@@ -13,17 +13,16 @@
 	reg_la0_data = 0b00; // [0] is low means stop reset
 
 	// Write
-  ((volatile uint32_t*) 0x30000000)[0] = 0x2400000F;
-  ((volatile uint32_t*) 0x30000000)[1] = 0x241000F0;
-  ((volatile uint32_t*) 0x30000000)[2] = 0x24200F00;
-  ((volatile uint32_t*) 0x30000000)[3] = 0x2430F000;
-  ((volatile uint32_t*) 0x30000000)[4] = 0x24400BAD;
-  ((volatile uint32_t*) 0x30000000)[5] = 0x24500B09;
-  ((volatile uint32_t*) 0x30000000)[6] = 0x30040000;
-  ((volatile uint32_t*) 0x30000000)[7] = 0x10640000;
-  ((volatile uint32_t*) 0x30000000)[8] = 0x31251100;
-  ((volatile uint32_t*) 0x30000000)[9] = 0x11751100;
-  ((volatile uint32_t*) 0x30000000)[10] = 0x50000000;
+  ((volatile uint32_t*) 0x30000000)[0] = 0x2400FF00;
+  ((volatile uint32_t*) 0x30000000)[1] = 0x10100000;
+  ((volatile uint32_t*) 0x30000000)[2] = 0x24200BA0;
+  ((volatile uint32_t*) 0x30000000)[3] = 0x24305000;
+  ((volatile uint32_t*) 0x30000000)[4] = 0x20303800;
+  ((volatile uint32_t*) 0x30000000)[5] = 0x30320000;
+  ((volatile uint32_t*) 0x30000000)[6] = 0x24400BA1;
+  ((volatile uint32_t*) 0x30000000)[7] = 0x34400010;
+  ((volatile uint32_t*) 0x30000000)[8] = 0x14500010;
+  ((volatile uint32_t*) 0x30000000)[9] = 0x90000003;
 
 	// Release control and reset
 	reg_la0_data = 0b11; // [1] is high means release control back to hs32

verilog/dv/caravel/hs32_soc/core1test7/test7_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v b/verilog/dv/caravel/hs32_soc/core1test7/test7_tb.v
similarity index 85%
rename from verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v
rename to verilog/dv/caravel/hs32_soc/core1test7/test7_tb.v
index 433d28e..7952d1a 100644
--- a/verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v
+++ b/verilog/dv/caravel/hs32_soc/core1test7/test7_tb.v
@@ -1,4 +1,5 @@
 `define DBG1
+`define LOG_MEMORY_WRITE
 
 `default_nettype none
 
@@ -8,6 +9,8 @@
 `include "spiflash.v"
 
 module tb();
+	parameter TEST_ID = 5;
+
 	reg clock;
   reg RSTB;
 	reg power1, power2;
@@ -65,12 +68,16 @@
 	end
 
 	initial begin
-	    // Some weak test cases
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[0] == 16'hCAFE);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[1] == 16'h5);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[2] == 16'hCAFE);
-	    $display("Test 1 [MOV, LDR, STR Variant 1] Passed Weak Cases");
-	    //$finish;
+	    // Test cases go here
+	end
+
+	always @(*) begin
+		if(tb.uut.mprj.core1.core.EXEC.fault) begin
+			$display("%c[1;31m",27);
+			$display("Test %d: Faulted!", TEST_ID);
+			$display("%c[0m",27);
+			$finish;
+		end
 	end
 
 	always @(mprj_io) begin
@@ -114,7 +121,7 @@
 	);
 
 	spiflash #(
-		.FILENAME("test1.hex")
+		.FILENAME("test7.hex")
 	) spiflash (
 		.csb(flash_csb),
 		.clk(flash_clk),

verilog/dv/caravel/hs32_soc/core1test8/Makefile

diff --git a/verilog/dv/caravel/hs32_soc/core1test1.no/Makefile b/verilog/dv/caravel/hs32_soc/core1test8/Makefile
similarity index 93%
copy from verilog/dv/caravel/hs32_soc/core1test1.no/Makefile
copy to verilog/dv/caravel/hs32_soc/core1test8/Makefile
index 245b54a..5488205 100644
--- a/verilog/dv/caravel/hs32_soc/core1test1.no/Makefile
+++ b/verilog/dv/caravel/hs32_soc/core1test8/Makefile
@@ -9,7 +9,7 @@
 
 .SUFFIXES:
 
-PATTERN = test1
+PATTERN = test6
 
 all:  ${PATTERN:=.vcd}
 
@@ -37,6 +37,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.idx
 
 .PHONY: clean hex all

verilog/dv/caravel/hs32_soc/core1test8/README.md

diff --git a/verilog/dv/caravel/hs32_soc/core1test1.no/README.md b/verilog/dv/caravel/hs32_soc/core1test8/README.md
similarity index 71%
rename from verilog/dv/caravel/hs32_soc/core1test1.no/README.md
rename to verilog/dv/caravel/hs32_soc/core1test8/README.md
index 4c5d2b2..7e554a4 100644
--- a/verilog/dv/caravel/hs32_soc/core1test1.no/README.md
+++ b/verilog/dv/caravel/hs32_soc/core1test8/README.md
@@ -1,4 +1,6 @@
-# HS32 Test Instruction 1
+# HS32 Example Instruction 6
+
+**General Test 1**
 
 The HS32 instruction format looks like this:
 
@@ -34,10 +36,10 @@
 MOV     R6_u, R2          ; R6_u = 0x0ADD
 
 MOV     R4, 0x0B09        ; Branch Address
-MOV     R5, high(COND1)   ; 0x2166
-MOV     R5, R5, 16        ; R5 <- (R5 << 16)
-MOV     R5, low(COND1)    ; 0x0000
-STR     R4, R5            ; [R4] <- R5
+MOV     R8, high(COND1)   ; 0x2166
+MOV     R8, R8, 16        ; R8 <- (R8 << 16)
+MOV     R8, low(COND1)    ; 0x0000
+STR     R4, R8            ; [R4] <- R8
 
 COND2:
 MOV     R6, R6_u          ; R6 <- R6_u
@@ -56,28 +58,42 @@
 ```hex
 0x 24 00 BE EF
 0x 24 10 0A DD
-0x 20 20 10 00
-0x 60 00 10 00
+0x 20 21 00 00
+0x 60 01 10 00
 0x 30 02 00 00
 0x 10 12 00 00
 
 0x 24 30 0B AD
 0x 24 50 22 62
-0x 20 50 58 00
+0x 20 50 51 00
 0x 24 50 00 00
 0x 30 53 00 00
 
-0x 24 40 0B AD
-0x 24 50 21 66
-0x 20 50 58 00
-0x 24 50 00 00
-0x 30 54 00 00
+0x 24 40 0B 09
+0x 24 80 21 66
+0x 20 80 81 00
+0x 24 80 00 00
+0x 30 84 00 00
 
 0x 68 00 10 00
-0x 52 00 0B AD
+0x 72 00 0B AD
 
 0x 68 01 20 00
-0x 59 00 0B 09
+0x 79 00 0B 09
 
-0x 20 70 68 00
+0x 20 70 61 00
+
+0x 50 00 00 00
 ```
+
+## Expected result
+
+- [x] `R0   = 0xB412`
+- [x] `R1   = 0xB412`
+- [x] `R2   = 0x0ADD`
+- [x] `R3   = 0x0BAD`
+- [ ] `R4   = 0x0B09`
+- [ ] `R5   = 0x21660000`
+- [ ] `R6   = 0x0ADD`
+- [ ] `R6_u = 0x0ADD`
+- [ ] `R7   = 0x0ADD0000`

verilog/dv/caravel/hs32_soc/core1test8/tb.gtkw

diff --git a/verilog/dv/caravel/hs32_soc/core1test8/tb.gtkw b/verilog/dv/caravel/hs32_soc/core1test8/tb.gtkw
new file mode 100644
index 0000000..bcaa546
--- /dev/null
+++ b/verilog/dv/caravel/hs32_soc/core1test8/tb.gtkw
@@ -0,0 +1,370 @@
+[*]
+[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
+[*] Fri Dec 18 19:17:22 2020
+[*]
+[dumpfile] "/data/caravel-hs32core/verilog/dv/caravel/hs32_soc/core1test6/dump.vcd"
+[dumpfile_mtime] "Fri Dec 18 18:47:04 2020"
+[dumpfile_size] 328739070
+[savefile] "/data/caravel-hs32core/verilog/dv/caravel/hs32_soc/core1test6/tb.gtkw"
+[timestart] 227809800
+[size] 1536 778
+[pos] -1 -1
+*-16.106964 227916000 230148000 228036000 227460000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] tb.
+[treeopen] tb.uut.
+[treeopen] tb.uut.mprj.
+[treeopen] tb.uut.mprj.core1.
+[treeopen] tb.uut.mprj.core1.core.
+[treeopen] tb.uut.mprj.core1.core.EXEC.
+[treeopen] tb.uut.mprj.sram0.
+[sst_width] 261
+[signals_width] 344
+[sst_expanded] 1
+[sst_vpaned_height] 223
+@800200
+-WBS
+@28
+tb.uut.mprj.wb_clk_i
+tb.uut.mprj.wb_rst_i
+tb.uut.mprj.wbs_ack_o
+@22
+tb.uut.mprj.wbs_adr_i[31:0]
+@28
+tb.uut.mprj.wbs_cyc_i
+@22
+tb.uut.mprj.wbs_dat_i[31:0]
+tb.uut.mprj.wbs_dat_o[31:0]
+tb.uut.mprj.wbs_sel_i[3:0]
+@28
+tb.uut.mprj.wbs_stb_i
+tb.uut.mprj.wbs_we_i
+@1000200
+-WBS
+@28
+tb.uut.mprj.core1.ram_ce
+tb.uut.mprj.core1.bsy
+tb.uut.mprj.sram0.csb0
+tb.uut.mprj.sram0.csb0_reg
+@22
+tb.uut.mprj.dtw_e[15:0]
+tb.uut.mprj.dtw_n[15:0]
+@c00200
+-PQ
+@22
+tb.uut.mprj.core1.core.FETCH.\fifo[0][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[1][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[2][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[3][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[4][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[5][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[6][31:0]
+tb.uut.mprj.core1.core.FETCH.\fifo[7][31:0]
+@1401200
+-PQ
+@c00200
+-Fetch
+@28
+tb.uut.mprj.core1.core.FETCH.clk
+@22
+tb.uut.mprj.core1.core.FETCH.addr[31:0]
+tb.uut.mprj.core1.core.FETCH.dtr[31:0]
+@28
+tb.uut.mprj.core1.core.FETCH.ackm
+tb.uut.mprj.core1.core.FETCH.flush
+@22
+tb.uut.mprj.core1.core.FETCH.newpc[31:0]
+tb.uut.mprj.core1.core.FETCH.instd[31:0]
+@1401200
+-Fetch
+@c00200
+-BRAM CTL
+@22
+tb.uut.mprj.core1.bram_ctl.i_addr[11:0]
+@28
+tb.uut.mprj.core1.bram_ctl.i_clk
+@22
+tb.uut.mprj.core1.bram_ctl.i_dwrite[31:0]
+@28
+tb.uut.mprj.core1.bram_ctl.i_reset
+tb.uut.mprj.core1.bram_ctl.i_rw
+[color] 3
+tb.uut.mprj.core1.bram_ctl.i_stb
+[color] 3
+tb.uut.mprj.core1.bram_ctl.o_ack
+@22
+tb.uut.mprj.core1.bram_ctl.o_dread[31:0]
+@28
+tb.uut.mprj.core1.bram_ctl.r_bsy
+@200
+-
+@22
+tb.uut.mprj.core1.bram_ctl.r_dread[31:0]
+tb.uut.mprj.core1.bram_ctl.dbuf[31:0]
+tb.uut.mprj.core1.bram_ctl.wbuf[31:0]
+@200
+-
+@22
+tb.uut.mprj.core1.bram_ctl.a0[9:0]
+tb.uut.mprj.core1.bram_ctl.a1[9:0]
+tb.uut.mprj.core1.bram_ctl.a2[9:0]
+tb.uut.mprj.core1.bram_ctl.a3[9:0]
+tb.uut.mprj.core1.bram_ctl.cpu_addr_e[15:0]
+tb.uut.mprj.core1.bram_ctl.cpu_addr_n[15:0]
+tb.uut.mprj.core1.bram_ctl.dbuf0[31:0]
+tb.uut.mprj.core1.bram_ctl.dbuf1[31:0]
+tb.uut.mprj.core1.bram_ctl.dbuf2[31:0]
+tb.uut.mprj.core1.bram_ctl.dbuf3[31:0]
+@1401200
+-BRAM CTL
+@800200
+-Decode
+@28
+tb.uut.mprj.core1.core.DECODE.clk
+tb.uut.mprj.core1.core.DECODE.reset
+@22
+tb.uut.mprj.core1.core.DECODE.int_line[23:0]
+@28
+[color] 3
+tb.uut.mprj.core1.core.DECODE.reqd
+[color] 3
+tb.uut.mprj.core1.core.DECODE.rdyd
+@200
+-
+@28
+[color] 3
+tb.uut.mprj.core1.core.DECODE.reqe
+[color] 3
+tb.uut.mprj.core1.core.DECODE.rdye
+@29
+tb.uut.mprj.core1.core.DECODE.r_hasnext
+@200
+-
+@22
+tb.uut.mprj.core1.core.DECODE.instd[31:0]
+@200
+-
+@22
+tb.uut.mprj.core1.core.DECODE.aluop[3:0]
+@28
+tb.uut.mprj.core1.core.DECODE.bank[1:0]
+@22
+tb.uut.mprj.core1.core.DECODE.ctlsig[15:0]
+tb.uut.mprj.core1.core.DECODE.imm[15:0]
+tb.uut.mprj.core1.core.DECODE.rd[3:0]
+tb.uut.mprj.core1.core.DECODE.rm[3:0]
+tb.uut.mprj.core1.core.DECODE.rn[3:0]
+tb.uut.mprj.core1.core.DECODE.shift[4:0]
+@1000200
+-Decode
+@800200
+-Execute
+@28
+tb.uut.mprj.core1.core.EXEC.clk
+[color] 3
+tb.uut.mprj.core1.core.EXEC.req
+[color] 3
+tb.uut.mprj.core1.core.EXEC.rdy
+@22
+tb.uut.mprj.core1.core.EXEC.state[3:0]
+@28
+tb.uut.mprj.core1.core.EXEC.fault
+tb.uut.mprj.core1.core.EXEC.int_inval
+@22
+tb.uut.mprj.core1.core.EXEC.control[54:0]
+tb.uut.mprj.core1.core.EXEC.r_control[54:0]
+@800200
+-Module I/O
+@28
+tb.uut.mprj.core1.core.EXEC.flush
+@22
+tb.uut.mprj.core1.core.EXEC.newpc[31:0]
+@200
+-
+@22
+tb.uut.mprj.core1.core.EXEC.aluop[3:0]
+tb.uut.mprj.core1.core.EXEC.shift[4:0]
+tb.uut.mprj.core1.core.EXEC.imm[15:0]
+tb.uut.mprj.core1.core.EXEC.rd[3:0]
+tb.uut.mprj.core1.core.EXEC.rm[3:0]
+tb.uut.mprj.core1.core.EXEC.rn[3:0]
+@28
+tb.uut.mprj.core1.core.EXEC.ctlsig[15:0]
+tb.uut.mprj.core1.core.EXEC.bank[1:0]
+@200
+-
+@28
+[color] 3
+tb.uut.mprj.core1.core.EXEC.stbm
+[color] 3
+tb.uut.mprj.core1.core.EXEC.ackm
+[color] 3
+tb.uut.mprj.core1.core.EXEC.stlm
+@22
+tb.uut.mprj.core1.core.EXEC.addr[31:0]
+tb.uut.mprj.core1.core.EXEC.dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtwm[31:0]
+@28
+[color] 3
+tb.uut.mprj.core1.core.EXEC.rw_mem
+@200
+-
+@28
+tb.uut.mprj.core1.core.EXEC.intrq
+@1000200
+-Module I/O
+@c00200
+-Internal Bus
+@22
+tb.uut.mprj.core1.core.EXEC.ibus1[31:0]
+tb.uut.mprj.core1.core.EXEC.ibus2[31:0]
+tb.uut.mprj.core1.core.EXEC.obus[31:0]
+tb.uut.mprj.core1.core.EXEC.aluout[31:0]
+@1401200
+-Internal Bus
+@800200
+-ALU
+@22
+tb.uut.mprj.core1.core.EXEC.alu_nzcv[3:0]
+@28
+tb.uut.mprj.core1.core.EXEC.alu_nzcv_out[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.carry
+@22
+tb.uut.mprj.core1.core.EXEC.alu.i_a[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_b[31:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.i_op[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_fl[3:0]
+tb.uut.mprj.core1.core.EXEC.alu.o_r[31:0]
+@1000200
+-ALU
+@800200
+-Special Registers
+@22
+tb.uut.mprj.core1.core.EXEC.r_dtrm[31:0]
+tb.uut.mprj.core1.core.EXEC.dtw[31:0]
+tb.uut.mprj.core1.core.EXEC.mar[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_s[31:0]
+tb.uut.mprj.core1.core.EXEC.pc_u[31:0]
+tb.uut.mprj.core1.core.EXEC.lr_i[31:0]
+tb.uut.mprj.core1.core.EXEC.sp_i[31:0]
+tb.uut.mprj.core1.core.EXEC.mcr_s[31:0]
+@28
+tb.uut.mprj.core1.core.EXEC.flags[31:0]
+@1000200
+-Special Registers
+@c00200
+-Register Control
+@28
+tb.uut.mprj.core1.core.EXEC.reg_we
+tb.uut.mprj.core1.core.EXEC.reg_we_s
+tb.uut.mprj.core1.core.EXEC.reg_we_u
+@200
+-
+@22
+tb.uut.mprj.core1.core.EXEC.regadra[3:0]
+tb.uut.mprj.core1.core.EXEC.regouta[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regouta_u[31:0]
+@200
+-
+@22
+tb.uut.mprj.core1.core.EXEC.regadrb[3:0]
+tb.uut.mprj.core1.core.EXEC.regoutb[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_s[31:0]
+tb.uut.mprj.core1.core.EXEC.regoutb_u[31:0]
+@1401200
+-Register Control
+@c00200
+-Supervisor Regfile
+@22
+tb.uut.mprj.core1.core.EXEC.regfile_s.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_s.\regs[15][31:0]
+@1401200
+-Supervisor Regfile
+@c00200
+-User Regfile
+@22
+tb.uut.mprj.core1.core.EXEC.regfile_u.wadr[3:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[0][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[1][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[2][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[3][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[4][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[5][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[6][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[7][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[8][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[9][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[10][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[11][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[12][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[13][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[14][31:0]
+tb.uut.mprj.core1.core.EXEC.regfile_u.\regs[15][31:0]
+@1401200
+-User Regfile
+@1000200
+-Execute
+@c00200
+-sram0
+@22
+tb.uut.mprj.sram0.addr0[7:0]
+@28
+tb.uut.mprj.sram0.clk0
+tb.uut.mprj.sram0.csb0
+@22
+tb.uut.mprj.sram0.din0[31:0]
+tb.uut.mprj.sram0.dout0[31:0]
+@28
+tb.uut.mprj.sram0.web0
+tb.uut.mprj.sram0.wmask0[3:0]
+@1401200
+-sram0
+@c00200
+-sram1
+@22
+tb.uut.mprj.sram1.addr0[7:0]
+@28
+tb.uut.mprj.sram1.clk0
+tb.uut.mprj.sram1.csb0
+@22
+tb.uut.mprj.sram1.din0[31:0]
+tb.uut.mprj.sram1.dout0[31:0]
+@28
+tb.uut.mprj.sram1.web0
+@22
+tb.uut.mprj.sram1.wmask0[3:0]
+@1401200
+-sram1
+@c00200
+-sram3
+@22
+tb.uut.mprj.sram2.addr0[7:0]
+@28
+tb.uut.mprj.sram2.clk0
+tb.uut.mprj.sram2.csb0
+@22
+tb.uut.mprj.sram2.din0[31:0]
+tb.uut.mprj.sram2.dout0[31:0]
+@28
+tb.uut.mprj.sram2.web0
+tb.uut.mprj.sram2.wmask0[3:0]
+@1401200
+-sram3
+[pattern_trace] 1
+[pattern_trace] 0

verilog/dv/caravel/hs32_soc/core1test8/test6.c

diff --git a/verilog/dv/caravel/hs32_soc/core1test8/test6.c b/verilog/dv/caravel/hs32_soc/core1test8/test6.c
new file mode 100644
index 0000000..f02cd94
--- /dev/null
+++ b/verilog/dv/caravel/hs32_soc/core1test8/test6.c
@@ -0,0 +1,56 @@
+#include "../../defs.h"
+
+void main()
+{
+	// Reset
+	reg_la0_ena = 0x00000000;    // [31:0]
+	reg_la1_ena = 0xFFFFFFFF;    // [63:32]
+	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
+	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
+	
+	// Reset and control bus
+	reg_la0_data = 0b01; // [0] is high means reset
+	reg_la0_data = 0b00; // [0] is low means stop reset
+
+	// Write
+  ((volatile uint32_t*) 0x30000000)[0] = 0x2400BEEF;
+  ((volatile uint32_t*) 0x30000000)[1] = 0x24100ADD;
+  ((volatile uint32_t*) 0x30000000)[2] = 0x20210000;
+  ((volatile uint32_t*) 0x30000000)[3] = 0x60011000;
+  ((volatile uint32_t*) 0x30000000)[4] = 0x30020000;
+  ((volatile uint32_t*) 0x30000000)[5] = 0x10120000;
+  ((volatile uint32_t*) 0x30000000)[6] = 0x24300BAD;
+  ((volatile uint32_t*) 0x30000000)[7] = 0x24502262;
+  ((volatile uint32_t*) 0x30000000)[8] = 0x20505100;
+  ((volatile uint32_t*) 0x30000000)[9] = 0x24500000;
+  ((volatile uint32_t*) 0x30000000)[10] = 0x30530000;
+  ((volatile uint32_t*) 0x30000000)[11] = 0x24400B09;
+  ((volatile uint32_t*) 0x30000000)[12] = 0x24802166;
+  ((volatile uint32_t*) 0x30000000)[13] = 0x20808100;
+  ((volatile uint32_t*) 0x30000000)[14] = 0x24800000;
+  ((volatile uint32_t*) 0x30000000)[15] = 0x30840000;
+  ((volatile uint32_t*) 0x30000000)[16] = 0x68001000;
+  ((volatile uint32_t*) 0x30000000)[17] = 0x72000BAD;
+  ((volatile uint32_t*) 0x30000000)[18] = 0x68012000;
+  ((volatile uint32_t*) 0x30000000)[19] = 0x79000B09;
+  ((volatile uint32_t*) 0x30000000)[20] = 0x20706100;
+
+	// Release control and reset
+	reg_la0_data = 0b11; // [1] is high means release control back to hs32
+	reg_la0_data = 0b10;
+
+	// Configure lower 8-IOs as user output
+	// Observe counter value in the testbench
+	reg_mprj_io_0 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_1 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_2 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_3 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_4 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_5 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_6 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_7 =  GPIO_MODE_USER_STD_OUTPUT;
+
+  // Apply configuration
+  reg_mprj_xfer = 1;
+  while (reg_mprj_xfer == 1);
+}

verilog/dv/caravel/hs32_soc/core1test8/test6_tb.v

diff --git a/verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v b/verilog/dv/caravel/hs32_soc/core1test8/test6_tb.v
similarity index 82%
copy from verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v
copy to verilog/dv/caravel/hs32_soc/core1test8/test6_tb.v
index 433d28e..05b86f2 100644
--- a/verilog/dv/caravel/hs32_soc/core1test2/test1_tb.v
+++ b/verilog/dv/caravel/hs32_soc/core1test8/test6_tb.v
@@ -8,13 +8,15 @@
 `include "spiflash.v"
 
 module tb();
+	parameter TEST_ID = 6;
+
 	reg clock;
-  reg RSTB;
+  	reg RSTB;
 	reg power1, power2;
 	reg power3, power4;
 
-  wire gpio;
-  wire [37:0] mprj_io;
+  	wire gpio;
+  	wire [37:0] mprj_io;
 	wire [7:0] mprj_io_0;
 
 	assign mprj_io_0 = mprj_io[7:0];
@@ -65,12 +67,16 @@
 	end
 
 	initial begin
-	    // Some weak test cases
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[0] == 16'hCAFE);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[1] == 16'h5);
-	    wait(tb.uut.mprj.core1.core1.EXEC.regfile_s.regs[2] == 16'hCAFE);
-	    $display("Test 1 [MOV, LDR, STR Variant 1] Passed Weak Cases");
-	    //$finish;
+	    // Test cases go here
+	end
+
+	always @(*) begin
+		if(tb.uut.mprj.core1.core.EXEC.fault) begin
+			$display("%c[1;31m",27);
+			$display("Test %d: Faulted!", TEST_ID);
+			$display("%c[0m",27);
+			$finish;
+		end
 	end
 
 	always @(mprj_io) begin
@@ -105,7 +111,7 @@
 		.vssd2	  (VSS),
 		.clock	  (clock),
 		.gpio     (gpio),
-        .mprj_io  (mprj_io),
+    .mprj_io  (mprj_io),
 		.flash_csb(flash_csb),
 		.flash_clk(flash_clk),
 		.flash_io0(flash_io0),
@@ -114,7 +120,7 @@
 	);
 
 	spiflash #(
-		.FILENAME("test1.hex")
+		.FILENAME("test6.hex")
 	) spiflash (
 		.csb(flash_csb),
 		.clk(flash_clk),

verilog/rtl/hs32_user_proj/dev_filter.v

diff --git a/verilog/rtl/hs32_user_proj/dev_filter.v b/verilog/rtl/hs32_user_proj/dev_filter.v
new file mode 100644
index 0000000..6713925
--- /dev/null
+++ b/verilog/rtl/hs32_user_proj/dev_filter.v
@@ -0,0 +1,26 @@
+// TODO: Hahaha too lazy to do it
+module dev_filter (
+    input wire clk,
+    input wire rst,
+    input wire a,
+    output wire b,
+    output reg rise,
+    output reg fall
+);
+    reg[1:0] sync;
+    assign b = sync[1];
+
+    always @(posedge clk) if(rst) begin
+        sync <= 0;
+    end else begin
+        sync <= { sync[0], a };
+    end
+    
+    always @(posedge clk) if(rst) begin
+        rise <= 0;
+        fall <= 0;
+    end else begin
+        rise <= sync == 2'b01;
+        fall <= sync == 2'b10;
+    end
+endmodule
\ No newline at end of file

verilog/rtl/hs32_user_proj/dev_intercon.v

diff --git a/verilog/rtl/hs32_user_proj/dev_intercon.v b/verilog/rtl/hs32_user_proj/dev_intercon.v
new file mode 100644
index 0000000..f3a6c15
--- /dev/null
+++ b/verilog/rtl/hs32_user_proj/dev_intercon.v
@@ -0,0 +1,98 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+module dev_intercon (
+    input   wire clk,
+    input   wire reset,
+
+    // Controller interface
+    // rw and dtw are connected to all devices
+    input   wire i_stb,
+    output  wire o_ack,
+    input   wire[31:0] i_addr,
+    output  wire[31:0] o_dtr,
+    input   wire[31:0] i_dtw,
+    input   wire i_rw,
+
+    // Devices interface
+    input   wire[32*NS-1:0] i_dtr,
+    input   wire[NS-1:0] i_ack,
+    output  wire[NS-1:0] o_stb,
+    output  wire[MASK_LEN-1:0] o_addr,
+
+    // SRAM Interface
+    output wire sstb,
+    input  wire sack,
+    input  wire[31:0] sdtr
+);
+    parameter NS = 4;
+    parameter[MASK_LEN*NS-1:0] BASE = {
+        { 2'b00, 8'b0 },
+        { 2'b01, 8'b0 },
+        { 2'b10, 8'b0 },
+        { 2'b11, 8'b0 }
+    };
+    parameter[MASK_LEN*NS-1:0] MASK = {
+        { 2'b11, 8'b0 },
+        { 2'b11, 8'b0 },
+        { 2'b11, 8'b0 },
+        { 2'b11, 8'b0 }
+    };
+    parameter MASK_LEN = 10;
+
+    reg[31:0] aict_base;
+    reg[31:0] r_dtr;
+    wire[NS-1:0] sel;
+    wire none = ~(|sel);
+    wire in_aict = aict_base[31:MASK_LEN] == i_addr[31:MASK_LEN];
+
+    // Address decoder
+    genvar i;
+    generate
+        for(i = 0; i < NS; i = i+1) begin
+            assign sel[i] =
+                in_aict &&
+                ((i_addr[0+:MASK_LEN] & MASK[i*MASK_LEN+:MASK_LEN])
+                    == BASE[i*MASK_LEN+:MASK_LEN]);
+        end
+    endgenerate
+
+    assign o_addr = i_addr[0+:MASK_LEN];
+
+    // Data selector
+    integer j;
+    always @(*) begin
+        r_dtr = 32'b0;
+        for(j = 0; j < 32 * NS; j = j+1)
+            r_dtr[j%32] = r_dtr[j%32] | (sel[j/32] & i_dtr[j]);
+    end
+    assign o_dtr = none ? sdtr : i_addr == aict_base ? aict_base : r_dtr;
+
+    // Other signals
+    assign o_ack = none ? sack : |(i_ack & sel);
+    assign o_stb = { NS{ i_stb } } & sel;
+    assign sstb = none & i_stb;
+
+    // AICT base register
+    always @(posedge clk) if(reset) begin
+        aict_base <= 32'h0000_FF00;
+    end else if(i_addr == aict_base && i_stb && i_rw) begin
+        aict_base <= i_dtw;
+        `ifdef SIM
+            $display($time, " AICT moved to %X", i_dtw);
+        `endif
+    end
+endmodule

verilog/rtl/hs32_user_proj/dev_timer.v

diff --git a/verilog/rtl/hs32_user_proj/dev_timer.v b/verilog/rtl/hs32_user_proj/dev_timer.v
new file mode 100644
index 0000000..3d9e09a
--- /dev/null
+++ b/verilog/rtl/hs32_user_proj/dev_timer.v
@@ -0,0 +1,122 @@
+module dev_timer (
+    input   wire clk,
+    input   wire reset,
+
+    // Config
+    input   wire[2:0] clk_source,
+    input   wire[1:0] timer_mode,
+    input   wire[1:0] output_mode,
+
+    // Registers
+    input   wire[TIMER_BITS-1:0] match,
+
+    // Outputs
+    output  reg  int_match,
+    output  wire io,
+
+    // Pulse for 1T if I/O risen/fallen
+    input wire io_risen,
+    input wire io_fallen
+);
+    parameter TIMER_BITS = 16;
+
+`define TIMER_MODE_CTC      1
+`define TIMER_MODE_SPWM     2 // Single edge PWM
+`define TIMER_MODE_DPWM     3 // Dual edge PWM (rise/fall)
+`define TIMER_OUTPUT_TOGGLE 1
+`define TIMER_OUTPUT_INV    3
+
+    reg[TIMER_BITS-1:0] counter;
+    reg[9:0] divider;
+    reg direction; // 1 is ++
+
+    wire scale_clk =
+        clk_source == 1 ? 1 :
+        clk_source == 2 ? divider[2] : // scale clk 8
+        clk_source == 3 ? divider[5] : // scale clk 64
+        clk_source == 4 ? divider[7] : // scale clk 256
+        clk_source == 5 ? divider[9] : // scale clk 1024
+        clk_source == 6 ? io_risen :
+        clk_source == 7 ? io_fallen : 0;
+    wire timer_match = match == counter;
+    wire timer_ovf = & counter;
+
+    reg io_normal, io_spwm, io_dpwm;
+    wire io_output =
+        timer_mode == `TIMER_MODE_SPWM ? io_spwm :
+        timer_mode == `TIMER_MODE_DPWM ? io_dpwm : io_normal;
+    assign io = output_mode == `TIMER_OUTPUT_INV ? ~io_output : io_output;
+    
+    // Clock divider, drives: divider
+    always @(posedge clk) if(reset) begin
+        divider <= 0;
+    end else begin
+        divider <= divider + 1;
+    end
+
+    // Counter, drives: counter
+    always @(posedge clk) if(reset) begin
+        counter <= 0;
+    end else if(scale_clk) begin
+        if(timer_match && timer_mode == `TIMER_MODE_CTC) begin
+            counter <= 0;
+        end else begin
+            counter <=
+                timer_mode == `TIMER_MODE_DPWM && (counter == {TIMER_BITS{1'b1}} || !direction) ?
+                counter - 1 : counter + 1;
+        end
+    end
+
+    // Counter direction, drives: direction
+    always @(posedge clk) if(reset) begin
+        direction <= 1;
+    end else if(scale_clk) begin
+        if(timer_ovf && timer_mode == `TIMER_MODE_DPWM) begin
+            direction <= ~direction;
+        end else if(counter == 1) begin
+            direction <= 1;
+        end
+    end
+
+    // Timer output, drives: io_normal
+    always @(posedge clk) if(reset) begin
+        io_normal <= 0;
+    end else begin
+        if(timer_match) begin
+            io_normal <= output_mode == `TIMER_OUTPUT_TOGGLE ? ~io_normal : 1;
+        end
+    end
+
+    // Timer output, drives: io_spwm
+    always @(posedge clk) if(reset) begin
+        io_spwm <= 0;
+    end else begin
+        if(timer_match) begin
+            io_spwm <= 1;
+        end else if(timer_ovf) begin
+            io_spwm <= 0;
+        end
+    end
+
+    // Timer output, drives: io_dpwm
+    always @(posedge clk) if(reset) begin
+        io_dpwm <= 0;
+    end else begin
+        if(timer_match && direction) begin
+            io_dpwm <= 1;
+        end else if(timer_match && !direction) begin
+            io_dpwm <= 0;
+        end
+    end
+
+    // Interrupts, drive: int_match
+    always @(posedge clk) if(reset) begin
+        int_match <= 0;
+    end else begin
+        if(timer_match) begin
+            int_match <= 1;
+        end else begin
+            int_match <= 0;
+        end
+    end
+endmodule
\ No newline at end of file

verilog/rtl/hs32_user_proj/hs32_aic.v

diff --git a/verilog/rtl/hs32_user_proj/hs32_aic.v b/verilog/rtl/hs32_user_proj/hs32_aic.v
index 8a7fee8..f3a9e95 100644
--- a/verilog/rtl/hs32_user_proj/hs32_aic.v
+++ b/verilog/rtl/hs32_user_proj/hs32_aic.v
@@ -27,7 +27,7 @@
     // Memory interface in

     input   wire stb,

     output  wire ack,

-    input   wire[31:0] addr,

+    input   wire[9:0] addr,

     input   wire[31:0] dtw,

     output  wire[31:0] dtr,

     input   wire rw,

@@ -39,6 +39,7 @@
     output  wire[4:0] vec,          // Interrupt vector

     output  wire nmi                // Non maskable interrupt

 );

+    assign ack = 1;

 

     // Advanced Interrupt Controller Table

     reg[31:0] aict[23:0];

@@ -78,10 +79,10 @@
     assign handler = aict[vec] & (~32'b1111);

 

     // Calculate table index

-    wire[4:0] aict_idx = addr[4:0]-1;

+    wire[4:0] aict_idx = addr[6:2]-1;

 

     // 1 clock cycle

-    assign ack = stb;

+    // assign ack = stb;

     assign dtr = aict[aict_idx];

 

     // Reset and write

@@ -91,5 +92,8 @@
             aict[i] <= 0;

     end else if(stb && rw) begin

         aict[aict_idx] <= dtw;

+        `ifdef SIM

+            $display($time, " AICT write %X <- %X", aict_idx, dtw);

+        `endif

     end

 endmodule

verilog/rtl/hs32_user_proj/hs32_core1.v

diff --git a/verilog/rtl/hs32_user_proj/hs32_core1.v b/verilog/rtl/hs32_user_proj/hs32_core1.v
index 498fc20..83f0405 100644
--- a/verilog/rtl/hs32_user_proj/hs32_core1.v
+++ b/verilog/rtl/hs32_user_proj/hs32_core1.v
@@ -1,8 +1,32 @@
+/**
+ * Copyright (c) 2020 The HSC Core Authors
+ * 
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ * 
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License. SPDX-License-Identifier: Apache-2.0
+ * 
+ * @file   hs32_core1.v
+ * @author Kevin Dai <kevindai02@outlook.com>
+ * @date   Created on December 16 2020, 12:25 AM
+ */
+
 `ifdef verilator
     `include "defines.v"
     `include "cpu/hs32_cpu.v"
+
+    `include "hs32_user_proj/hs32_aic.v"
     `include "hs32_user_proj/hs32_bram_ctl.v"
-    `include "frontend/mmio.v"
+    `include "hs32_user_proj/dev_filter.v"
+    `include "hs32_user_proj/dev_timer.v"
+    `include "hs32_user_proj/dev_intercon.v"
 `endif
 
 `default_nettype none
@@ -32,14 +56,14 @@
     output wire [31:0] wbs_dat_o,
 
     // Logic Analyzer Signals
-    input  wire [127:0] la_data_in,
-    output wire [127:0] la_data_out,
-    input  wire [127:0] la_oen,
+    input  wire [1:0] la_data_in,
+    // output wire [127:0] la_data_out,
+    input  wire [1:0] la_oen,
 
     // IOs
-    /*input  wire [`MPRJ_IO_PADS-1:0] io_in,
-    output wire [`MPRJ_IO_PADS-1:0] io_out,
-    output wire [`MPRJ_IO_PADS-1:0] io_oeb,*/
+    input  wire [`MPRJ_IO_PADS-1:0] io_in,
+    output reg  [`MPRJ_IO_PADS-1:0] io_out,
+    output reg  [`MPRJ_IO_PADS-1:0] io_oeb,
     
     // Output (north and east faces)
     output wire [7:0]  cpu_mask_n,
@@ -70,11 +94,6 @@
     // wire clk = (~la_oen[64])? la_data_in[64] : wb_clk_i;
     wire clk = wb_clk_i;
     wire rst = (~la_oen[0]) ? la_data_in[0] : wb_rst_i;
-    wire bus_hold = !(~la_oen[1] & la_data_in[1]);
-
-    // Wishbone logic
-    wire wb_stb = wbs_cyc_i && wbs_stb_i; 
-    wire wb_rw = |wbs_sel_i & wbs_we_i;
     
     //===============================//
     // Main CPU core
@@ -85,7 +104,7 @@
 
     hs32_cpu #(
         .IMUL(1), .BARREL_SHIFTER(1), .PREFETCH_SIZE(3)
-    ) core1 (
+    ) core (
         .i_clk(clk), .reset(rst),
 
         .addr(cpu_addr), .rw(cpu_rw),
@@ -104,6 +123,12 @@
     // Caravel + CPU Memory Bus
     //===============================//
 
+    // Wishbone logic
+    wire bus_hold = !(~la_oen[1] & la_data_in[1]);
+    wire wb_stb = wbs_cyc_i && wbs_stb_i; 
+    wire wb_rw = |wbs_sel_i & wbs_we_i;
+
+    // Bus multiplexer (caravel and main core)
     wire[31:0] addr, dread, dwrite;
     wire rw, stb, ack;
     assign stb      = bus_hold ? wb_stb : cpu_stb;
@@ -115,27 +140,67 @@
     assign wbs_ack_o = bus_hold ? ack : 0;
     assign cpu_ack = bus_hold ? 0: ack;
 
-    reg bsy;
-    assign ram_ce = ~(stb | bsy);
+    reg ram_bsy;
+    assign ram_ce = ~(ram_stb | ram_bsy);
     always @(posedge clk) if(rst)
-        bsy <= 0;
+        ram_bsy <= 0;
     else begin
-        if(stb && !bsy) begin
-            bsy <= 1;
-        end else if(ack && bsy) begin
-            bsy <= 0;
-`ifndef DBG1
-            if(rw) begin
-                $display($time, " Writing %X %X", addr, dwrite);
-            end else begin
-                $display($time, " Reading %X %X", addr, dread);
-            end
-`endif
+        if(ram_stb && !ram_bsy) begin
+            ram_bsy <= 1;
+        end else if(ram_ack && ram_bsy) begin
+            ram_bsy <= 0;
         end
     end
 
+    `ifdef SIM
+        reg bsy;
+        always @(posedge clk) if(rst)
+            bsy <= 0;
+        else if(stb && !bsy) begin
+            bsy <= 1;
+        end else if(ack && bsy) begin
+            bsy <= 0;
+            `ifdef LOG_MEMORY_WRITE
+                if(rw) $display($time, " Writing [%X] <- %X", addr, dwrite);
+            `endif
+            `ifdef LOG_MEMORY_READ
+                if(!rw) $display($time, " Reading [%X] -> %X", addr, dread);
+            `endif
+        end
+    `endif
+
     //===============================//
-    // MMIO and Interrupts
+    // Memory bus interconnect
+    //===============================//
+
+    wire [31:0] aic_dtr, sr0_dtr, sr1_dtr;
+    reg  [31:0] gpt_dtr;
+    wire aic_ack, gpt_ack, sr0_ack, sr1_ack;
+    wire aic_stb, gpt_stb, sr0_stb, sr1_stb;
+    wire[9:0] mmio_addr;
+    dev_intercon mmio_conn (
+        .clk(clk), .reset(rst),
+        
+        // Input
+        .i_stb(stb), .o_ack(ack),
+        .i_addr(addr), .o_dtr(dread),
+        .i_rw(rw), .i_dtw(dwrite),
+
+        // Devices
+        .i_dtr({ sr1_dtr, sr0_dtr, gpt_dtr, aic_dtr }),
+        .i_ack({ sr1_ack, sr0_ack, gpt_ack, aic_ack }),
+        .o_stb({ sr1_stb, sr0_stb, gpt_stb, aic_stb }),
+        .o_addr(mmio_addr),
+
+        // SRAM
+        .sstb(ram_stb), .sack(ram_ack), .sdtr(ram_dread)
+    );
+    assign ram_rw = rw;
+    assign ram_addr = addr;
+    assign ram_dwrite = dwrite;
+
+    //===============================//
+    // Interrupts
     //===============================//
 
     wire [23:0] inte;
@@ -143,23 +208,139 @@
     wire [31:0] isr;
     wire irq, nmi;
 
-    mmio #(
-        .AICT_NUM_RE(1), .AICT_NUM_RI(1)
-    ) mmio_unit (
+    hs32_aic aict (
         .clk(clk), .reset(rst),
-        // CPU
-        .stb(stb), .ack(ack),
-        .addr(addr), .dtw(dwrite), .dtr(dread), .rw(rw),
-        // RAM
-        .sstb(ram_stb), .sack(ram_ack), .srw(ram_rw),
-        .saddr(ram_addr), .sdtw(ram_dwrite), .sdtr(ram_dread),
+        // Bus
+        .stb(aic_stb), .ack(aic_ack),
+        .addr(mmio_addr), .dtw(dwrite),
+        .dtr(aic_dtr), .rw(rw),
         // Interrupt controller
-        .interrupts(inte), .handler(isr), .intrq(irq), .vec(ivec), .nmi(nmi),
-        // More registers
-        .aict_r(), .aict_w()
+        .interrupts(inte), .handler(isr),
+        .intrq(irq), .vec(ivec), .nmi(nmi)
     );
 
     //===============================//
+    // GPIO
+    //===============================//
+
+    localparam NUM_IO = `MPRJ_IO_PADS;
+    wire[NUM_IO-1:0] io_in_sync, io_in_rise, io_in_fall;
+
+    // Generate filter block
+    dev_filter filter[NUM_IO-1:0](
+        .clk(clk),
+        .rst(rst),
+        .a(io_in),
+        .b(io_in_sync),
+        .rise(io_in_rise),
+        .fall(io_in_fall)
+    );
+
+    assign gpt_ack = 1;
+    reg[75:0] io_int;
+    always @(posedge clk) if(rst) begin
+        io_out <= 0;
+        io_oeb <= 0;
+        io_int <= 0;
+    end else begin
+        if(gpt_stb && rw) case(mmio_addr)
+            0: begin end
+            1: io_out[31:0] <= dwrite;
+            2: io_out[37:32] <= dwrite[5:0];
+            3: io_oeb[31:0] <= dwrite;
+            4: io_oeb[37:32] <= dwrite[5:0];
+            5: io_int[31:0] <= dwrite;
+            6: io_int[63:32] <= dwrite;
+            7: io_int[75:64] <= dwrite[11:0];
+            default: begin end
+        endcase
+    end
+    always @(*) begin
+        case(mmio_addr)
+            0: begin end
+            1: gpt_dtr = io_out[31:0];
+            2: gpt_dtr = { 26'b0, io_out[37:32] };
+            3: gpt_dtr = io_oeb[31:0];
+            4: gpt_dtr = { 26'b0, io_oeb[37:32] };
+            5: gpt_dtr = io_int[31:0];
+            6: gpt_dtr = io_int[63:32];
+            7: gpt_dtr = { 20'b0, io_int[75:64] };
+            default: begin end
+        endcase
+    end
+
+    //===============================//
+    // Timer
+    //===============================//
+
+    localparam T0_IO_NUM = 15;
+    localparam T1_IO_NUM = 16;
+    localparam T2_IO_NUM = 17;
+
+    // Timer 0 (there has to be a better way to do this)
+    wire t0_match_int;
+    wire t0_io_out;
+    reg[7:0] t0_config;
+    reg[15:0] t0_match;
+    dev_timer #(
+        .TIMER_BITS(16)
+    ) dev_timer0 (
+        .clk(clk), .reset(rst),
+        .clk_source(t0_config[2:0]),
+        .timer_mode(t0_config[4:3]),
+        .output_mode(t0_config[6:5]),
+        .match(t0_match),
+        .int_match(t0_match_int),
+        .io(t0_io_out),
+        .io_risen(io_in_rise[T0_IO_NUM]),
+        .io_fallen(io_in_fall[T0_IO_NUM])
+    );
+
+    // Timer 1
+    wire t1_match_int;
+    wire t1_io_out;
+    reg[7:0] t1_config;
+    reg[15:0] t1_match;
+    dev_timer #(
+        .TIMER_BITS(16)
+    ) dev_timer1 (
+        .clk(clk), .reset(rst),
+        .clk_source(t1_config[2:0]),
+        .timer_mode(t1_config[4:3]),
+        .output_mode(t1_config[6:5]),
+        .match(t1_match),
+        .int_match(t1_match_int),
+        .io(t1_io_out),
+        .io_risen(io_in_rise[T1_IO_NUM]),
+        .io_fallen(io_in_fall[T1_IO_NUM])
+    );
+
+    // Timer 2
+    wire t2_match_int;
+    wire t2_io_out;
+    reg[7:0] t2_config;
+    reg[31:0] t2_match;
+    dev_timer #(
+        .TIMER_BITS(32)
+    ) dev_timer2 (
+        .clk(clk), .reset(rst),
+        .clk_source(t2_config[2:0]),
+        .timer_mode(t2_config[4:3]),
+        .output_mode(t2_config[6:5]),
+        .match(t2_match),
+        .int_match(t2_match_int),
+        .io(t2_io_out),
+        .io_risen(io_in_rise[T2_IO_NUM]),
+        .io_fallen(io_in_fall[T2_IO_NUM])
+    );
+
+    //===============================//
+    // UART
+    //===============================//
+
+
+
+    //===============================//
     // Internal SRAM controller
     //===============================//
 
@@ -186,4 +367,4 @@
         .dbuf1(cpu_dtr_e0),
         .dbuf0(cpu_dtr_e1)
     );
-endmodule
\ No newline at end of file
+endmodule

verilog/rtl/hs32_user_proj/hs32_intercon.v

diff --git a/verilog/rtl/hs32_user_proj/hs32_intercon.v b/verilog/rtl/hs32_user_proj/hs32_intercon.v
deleted file mode 100644
index 291efc4..0000000
--- a/verilog/rtl/hs32_user_proj/hs32_intercon.v
+++ /dev/null
@@ -1,36 +0,0 @@
-module hs32_intercon (
-    input   wire clk,
-    input   wire reset,
-
-    // Controller interface
-    input   wire stb,
-    output  wire ack,
-    input   wire[31:0] addr,
-    input   wire[31:0] dtw,
-    input   wire rw,
-
-    // Devices interface
-    input   wire[32*NS-1:0] dtr,
-    input   wire[NS-1:0] i_ack,
-    output  wire[NS-1:0] o_stb
-);
-    parameter NS = 4;
-    parameter[32*NS-1:0] MASK = {
-        { 27'b0, 5'b11111 },
-        { 27'b0, 5'b01111 },
-        { 24'b0, 8'hFF },
-        { 24'b0, 8'hFF }
-    };
-    parameter [32*NS-1:0] LIMITS = {
-        { 27'b0, 5'd25 }, // 24 + 1 base
-        { 27'b0, 5'd12 },
-        { 24'b0, 8'hFF },
-        { 24'b0, 8'hFF }
-    };
-    parameter BASE_MASK = 
-    
-    reg[31:0] aict_base;
-
-
-
-endmodule

verilog/rtl/hs32_user_proj/hs32_mpi.v

diff --git a/verilog/rtl/hs32_user_proj/hs32_filter.v b/verilog/rtl/hs32_user_proj/hs32_mpi.v
similarity index 100%
rename from verilog/rtl/hs32_user_proj/hs32_filter.v
rename to verilog/rtl/hs32_user_proj/hs32_mpi.v

verilog/rtl/hs32_user_proj/hs32_timer.v

diff --git a/verilog/rtl/hs32_user_proj/hs32_timer.v b/verilog/rtl/hs32_user_proj/hs32_timer.v
deleted file mode 100644
index 5aec73f..0000000
--- a/verilog/rtl/hs32_user_proj/hs32_timer.v
+++ /dev/null
@@ -1,36 +0,0 @@
-module hs32_timer(
-    input   wire clk,
-    input   wire reset,
-
-    // Config
-    input   wire[2:0] clk_source,
-    input   wire[1:0] timer_mode,
-    input   wire[1:0] output_mode,
-
-    // Registers
-    input   wire[31:0] match,
-
-    // Outputs
-    output  wire int_match,
-    output  wire io
-);
-    reg[31:0] counter;
-    reg[9:0] divider;
-
-    wire scale_clk8 = divider[2];
-    wire scale_clk64 = divider[5];
-    wire scale_clk256 = divider[7];
-    wire scale_clk1024 = divider[9];
-    
-    always @(posedge clk) if(reset) begin
-        divider <= 0;
-    end else begin
-        divider <= divider + 1;
-    end
-
-    always @(posedge clk) if(reset) begin
-        counter <= 0;
-    end else begin
-        
-    end
-endmodule
\ No newline at end of file

verilog/rtl/hs32_user_proj/hs32_wrapper.v

diff --git a/verilog/rtl/hs32_user_proj/hs32_wrapper.v b/verilog/rtl/hs32_user_proj/hs32_wrapper.v
index 9ef652f..c631fef 100644
--- a/verilog/rtl/hs32_user_proj/hs32_wrapper.v
+++ b/verilog/rtl/hs32_user_proj/hs32_wrapper.v
@@ -104,9 +104,8 @@
 
 	    // Logic Analyzer
 
-	    .la_data_in(la_data_in),
-	    .la_data_out(la_data_out),
-	    .la_oen (la_oen),
+	    .la_data_in(la_data_in[1:0]),
+	    .la_oen (la_oen[1:0]),
 
         // SRAM meme :3
         .cpu_mask_n(mask_n),

verilog/rtl/hs32cpu

diff --git a/verilog/rtl/hs32cpu b/verilog/rtl/hs32cpu
index ac451b2..48b1fe4 160000
--- a/verilog/rtl/hs32cpu
+++ b/verilog/rtl/hs32cpu
@@ -1 +1 @@
-Subproject commit ac451b2df2641a39ed52cb5c19752b8fe71eec0c
+Subproject commit 48b1fe43a14ee29dd3334086fa5f09c4318fcf53

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 44e8eda..c30ea37 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -14,6 +14,19 @@
 // SPDX-License-Identifier: Apache-2.0
 
 `default_nettype none
+
+`ifdef SIM
+    `include "cpu/hs32_cpu.v"
+    
+    `include "hs32_user_proj/hs32_core1.v"
+
+    `include "hs32_user_proj/hs32_aic.v"
+    `include "hs32_user_proj/hs32_bram_ctl.v"
+    `include "hs32_user_proj/dev_filter.v"
+    `include "hs32_user_proj/dev_timer.v"
+    `include "hs32_user_proj/dev_intercon.v"
+`endif
+
 /*
  *-------------------------------------------------------------
  *
@@ -34,7 +47,8 @@
  *
  *-------------------------------------------------------------
  */
-
+`ifndef SIM 
+`ifndef verilator
 module user_proj_example #(
     parameter BITS = 32
 )(
@@ -170,3 +184,5 @@
 
 endmodule
 `default_nettype wire
+`endif
+`endif

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 47d92f4..2a1e347 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -29,7 +29,9 @@
  *-------------------------------------------------------------
  */
 
-module user_project_wrapper #(
+`include "hs32_user_proj/hs32_wrapper.v"
+
+/*module user_project_wrapper #(
     parameter BITS = 32
 )(
 `ifdef USE_POWER_PINS
@@ -75,9 +77,9 @@
     input   user_clock2
 );
 
-    /*--------------------------------------*/
-    /* User project is instantiated  here   */
-    /*--------------------------------------*/
+    //--------------------------------------//
+    // User project is instantiated  here   //
+    //--------------------------------------//
 
     user_proj_example mprj (
     `ifdef USE_POWER_PINS
@@ -121,4 +123,6 @@
     );
 
 endmodule	// user_project_wrapper
+*/
+
 `default_nettype wire