Added the functionality to accept RX bits either from io pads or from the LA probes

verilog/rtl/ibtida-soc/Ibtida_top_dffram_cv.v

diff --git a/verilog/rtl/ibtida-soc/Ibtida_top_dffram_cv.v b/verilog/rtl/ibtida-soc/Ibtida_top_dffram_cv.v
index 5d75303..d9e8104 100644
--- a/verilog/rtl/ibtida-soc/Ibtida_top_dffram_cv.v
+++ b/verilog/rtl/ibtida-soc/Ibtida_top_dffram_cv.v
@@ -8725,7 +8725,7 @@
   assign clock = wb_clk_i;
   assign reset = (~la_oen[0]) ? (la_data_in[0]) : wb_rst_i;
   assign io_CLK_PER_BIT = la_data_in[47:32];
-  assign io_rx_i = io_in[5];
+  assign io_rx_i = (~la_oen[64]) ? (la_data_in[64]) : io_in[5];
   assign io_gpio_i = io_in[37:8];
   assign io_out[37:8] = io_gpio_o;
   assign io_oeb[37:8] = io_gpio_en_o;