Modified the test for verification

verilog/dv/caravel/user_proj_example/ibtida/ibtida_test.c

diff --git a/verilog/dv/caravel/user_proj_example/ibtida/ibtida_test.c b/verilog/dv/caravel/user_proj_example/ibtida/ibtida_test.c
index 12395e3..f714351 100644
--- a/verilog/dv/caravel/user_proj_example/ibtida/ibtida_test.c
+++ b/verilog/dv/caravel/user_proj_example/ibtida/ibtida_test.c
@@ -3,7 +3,7 @@
 void main()
 {
   // reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
-  // reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+   reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
   // reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
   // reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
   // reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;