checks/full_log.log

FULL RUN LOG:
 Uncompressing the gds files
Step 0 done without fatal errors.
 Executing Step 1 of 4: Checking License files.
{{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
 No third party libraries found.
Step 1 done without fatal errors.
{{SPDX COMPLIANCE WARNING}} Found 2576 non-compliant files with the SPDX Standard. Check full log for more information
SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/.travis.yml', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/mpw-one-a.md', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Makefile', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/chip_dimensions.txt', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/README.md', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/pdn.tcl', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/interactive.tcl.orig', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/ibtida_flow.tcl', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/config.tcl', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/src/Ibtida_top_dffram_cv.sdc', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/src/DFFRAM.v', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/src/Ibtida_top_dffram_cv.v', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/src/syn.sdc', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/src/DFFRAMBB.v', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/runs/Ibtida_top_dffram_cv/config.tcl', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/runs/Ibtida_top_dffram_cv/reports/runtime.txt', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/runs/Ibtida_top_dffram_cv/reports/placement/replace.rpt', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/runs/Ibtida_top_dffram_cv/reports/placement/replace.min_max.rpt', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/runs/Ibtida_top_dffram_cv/reports/placement/replace_tns.rpt', '/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/Ibtida_top_dffram_cv/runs/Ibtida_top_dffram_cv/reports/placement/replace.timing.rpt']
 Executing Step 2 of 4: Checking YAML description.
 YAML file valid!
Step 2 done without fatal errors.
 Executing Step 3 of 4: Executing Fuzzy Consistency Checks.
b'Going into /home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/verilog/rtl'
b'Removing manifest'
b'Fetching manifest'
b'Running sha1sum checks'
b'Going into /home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/maglef'
b'Removing manifest'
b'Fetching manifest'
b'Running sha1sum checks'
b'Going into /home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/mag'
b'Removing manifest'
b'Fetching manifest'
b'Running sha1sum checks'
 Manifest Checks Failed. Please rebase your Repository to the latest Caravel master.
caravel.v: FAILED
.magicrc: FAILED
 Documentation Checks Passed.
 Makefile Checks Passed.
instance caravel found
instance user_project_wrapper found
Design is complex and contains: 47 modules
Design is complex and contains: 2 modules
verilog Consistency Checks Passed.
 Basic Hierarchy Checks Passed.
 Running Magic Extractions From GDS...
user wrapper cell names differences: 
[]
user wrapper cell type differences: 
[]
toplevel cell names differences: 
[]
toplevel cell type differences: 
[]
GDS Hierarchy Check Passed
GDS Checks Passed
{PROGRESS} Running Pins and Power Checks...
Pins check passed
Internal Power Checks Passed!
 Fuzzy Consistency Checks Passed!
Step 3 done without fatal errors.
 Executing Step 4 of 4: Checking DRC Violations.
 Running DRC Checks...
Violation Message "Metal4 > 3um spacing to unrelated m4 < 0.4um (met4.5b) "found 2 Times.
Violation Message "Metal3 > 3um spacing to unrelated m3 < 0.4um (met3.3d) "found 2 Times.
Violation Message "Can't overlap those layers "found 2 Times.
Violation Message "Min area of metal2 holes > 0.14um^2 (met2.7) "found 20 Times.
Violation Message "Metal3 spacing < 0.3um (met3.2) "found 6 Times.
Violation Message "Metal3 width < 0.3um (met3.1) "found 1 Times.
Violation Message "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b) "found 17 Times.
Violation Message "Metal2 > 3um spacing to unrelated m2 < 0.28um (met2.3b) "found 21 Times.
 DRC Checks on MAG Failed, Reason: Total # of DRC violations is 71
TEST FAILED AT STEP 4