Files created by running the prechecker locally
diff --git a/checks/caravel.magic.drc.mag b/checks/caravel.magic.drc.mag
index 56152f6..3640df4 100644
--- a/checks/caravel.magic.drc.mag
+++ b/checks/caravel.magic.drc.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1608298075
+timestamp 1608321899
<< checkpaint >>
rect -3932 -3932 721532 1041532
<< metal1 >>
@@ -80930,9 +80930,9 @@
transform 1 0 0 0 1 0
box 0 0 717600 1037600
use user_project_wrapper mprj
-timestamp 1608298075
+timestamp 1608321899
transform 1 0 65308 0 1 278716
-box -2936 -1866 586860 705802
+box -8576 -7506 592500 711442
<< properties >>
string FIXED_BBOX 0 0 717600 1037600
<< end >>
diff --git a/checks/full_log.log b/checks/full_log.log
index db3d348..3c81235 100644
--- a/checks/full_log.log
+++ b/checks/full_log.log
@@ -24,6 +24,7 @@
b'Fetching manifest'
b'Running sha1sum checks'
Manifest Checks Failed. Please rebase your Repository to the latest Caravel master.
+caravel.v: FAILED
.magicrc: FAILED
Documentation Checks Passed.
Makefile Checks Passed.
diff --git a/checks/manifest_check.rtl.log b/checks/manifest_check.rtl.log
index d23a4dd..fe2fe19 100644
--- a/checks/manifest_check.rtl.log
+++ b/checks/manifest_check.rtl.log
@@ -1,5 +1,5 @@
caravel_clocking.v: OK
-caravel.v: OK
+caravel.v: FAILED
chip_io.v: OK
clock_div.v: OK
convert_gpio_sigs.v: OK
diff --git a/checks/spdx_compliance_report.log b/checks/spdx_compliance_report.log
index a80b194..5e42689 100644
--- a/checks/spdx_compliance_report.log
+++ b/checks/spdx_compliance_report.log
@@ -1658,9 +1658,9 @@
/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/DFFRAM/README.md
/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/DFFRAM/config.tcl
/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/user_project_wrapper/pdn.tcl
-/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/user_project_wrapper/pdn.tcl.updated
/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/user_project_wrapper/interactive.tcl
/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/user_project_wrapper/config.tcl
+/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/user_project_wrapper/gen_pdn.tcl
/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/user_project_wrapper/runs/user_project_wrapper_ADJUSTMENT_0.3/config.tcl
/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/user_project_wrapper/runs/user_project_wrapper_ADJUSTMENT_0.3/reports/floorplan/verilog2def.die_area.rpt
/home/hadirkhan10/Desktop/ibtida-soc-mpw-one-b/openlane/user_project_wrapper/runs/user_project_wrapper_ADJUSTMENT_0.3/reports/floorplan/verilog2def.core_area.rpt
