| commit | 08cd6eba30b5b59bbd33a808a9173203d7a7175b | [log] [tgz] |
|---|---|---|
| author | Matt Venn <matt@mattvenn.net> | Mon Nov 16 12:01:14 2020 +0100 |
| committer | Matt Venn <matt@mattvenn.net> | Mon Nov 16 12:01:14 2020 +0100 |
| tree | ed5d102ae14d7dca40e78ce0ae9a81ec0548cfd8 | |
| parent | d4cc669e6b40d8f170c2674fe18ae0f43093f0c3 [diff] [blame] |
add default nettype none
diff --git a/verilog/gl/digital_pll.v b/verilog/gl/digital_pll.v index 0b1f5ed..4310af0 100644 --- a/verilog/gl/digital_pll.v +++ b/verilog/gl/digital_pll.v
@@ -1,3 +1,4 @@ +`default_nettype none /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */ module digital_pll(dco, enable, osc, resetb, VPWR, VGND, clockp, div, ext_trim);