add default nettype none
diff --git a/verilog/gl/DFFRAM.v b/verilog/gl/DFFRAM.v
index c46f8d8..f0a55fe 100644
--- a/verilog/gl/DFFRAM.v
+++ b/verilog/gl/DFFRAM.v
@@ -1,3 +1,4 @@
+`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module DFFRAM(CLK, EN, VPWR, VGND, A, Di, Do, WE);
diff --git a/verilog/gl/digital_pll.v b/verilog/gl/digital_pll.v
index 0b1f5ed..4310af0 100644
--- a/verilog/gl/digital_pll.v
+++ b/verilog/gl/digital_pll.v
@@ -1,3 +1,4 @@
+`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module digital_pll(dco, enable, osc, resetb, VPWR, VGND, clockp, div, ext_trim);
diff --git a/verilog/gl/gpio_control_block.v b/verilog/gl/gpio_control_block.v
index 57c53f6..9796422 100644
--- a/verilog/gl/gpio_control_block.v
+++ b/verilog/gl/gpio_control_block.v
@@ -1,3 +1,4 @@
+`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module gpio_control_block(mgmt_gpio_in, mgmt_gpio_oeb, mgmt_gpio_out, pad_gpio_ana_en, pad_gpio_ana_pol, pad_gpio_ana_sel, pad_gpio_holdover, pad_gpio_ib_mode_sel, pad_gpio_in, pad_gpio_inenb, pad_gpio_out, pad_gpio_outenb, pad_gpio_slow_sel, pad_gpio_vtrip_sel, resetn, serial_clock, serial_data_in, serial_data_out, user_gpio_in, user_gpio_oeb, user_gpio_out, VPWR, VGND, pad_gpio_dm);
diff --git a/verilog/gl/simple_por.v b/verilog/gl/simple_por.v
index bf90099..2291444 100644
--- a/verilog/gl/simple_por.v
+++ b/verilog/gl/simple_por.v
@@ -1,3 +1,4 @@
+`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module simple_por(porb_h, vdd3v3, vss, VPWR, VGND);
diff --git a/verilog/gl/storage.v b/verilog/gl/storage.v
index e82d48b..a629e82 100644
--- a/verilog/gl/storage.v
+++ b/verilog/gl/storage.v
@@ -1,3 +1,4 @@
+`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module storage(mgmt_clk, mgmt_ena_ro, VPWR, VGND, mgmt_addr, mgmt_addr_ro, mgmt_ena, mgmt_rdata, mgmt_rdata_ro, mgmt_wdata, mgmt_wen, mgmt_wen_mask);
diff --git a/verilog/gl/user_id_programming.v b/verilog/gl/user_id_programming.v
index 715e184..b941b6b 100644
--- a/verilog/gl/user_id_programming.v
+++ b/verilog/gl/user_id_programming.v
@@ -1,3 +1,4 @@
+`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module user_id_programming(vdd1v8, vss, VPWR, VGND, mask_rev);
diff --git a/verilog/gl/user_proj_example.v b/verilog/gl/user_proj_example.v
index a80278b..74638c0 100644
--- a/verilog/gl/user_proj_example.v
+++ b/verilog/gl/user_proj_example.v
@@ -1,3 +1,4 @@
+`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module user_proj_example(vccd1, vccd2, vdda1, vdda2, vssa1, vssa2, vssd1, vssd2, wb_clk_i, wb_rst_i, wbs_ack_o, wbs_cyc_i, wbs_stb_i, wbs_we_i, VPWR, VGND, io_in, io_oeb, io_out, la_data_in, la_data_out, la_oen, wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i);
