[LICENSE] used addlicense to add licenses to all source files
diff --git a/verilog/gl/gpio_control_block.v b/verilog/gl/gpio_control_block.v
index 30ac390..7ef8381 100644
--- a/verilog/gl/gpio_control_block.v
+++ b/verilog/gl/gpio_control_block.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module gpio_control_block(mgmt_gpio_in, mgmt_gpio_oeb, mgmt_gpio_out, pad_gpio_ana_en, pad_gpio_ana_pol, pad_gpio_ana_sel, pad_gpio_holdover, pad_gpio_ib_mode_sel, pad_gpio_in, pad_gpio_inenb, pad_gpio_out, pad_gpio_outenb, pad_gpio_slow_sel, pad_gpio_vtrip_sel, resetn, serial_clock, serial_data_in, serial_data_out, user_gpio_in, user_gpio_oeb, user_gpio_out, VPWR, VGND, pad_gpio_dm);
