[LICENSE] used addlicense to add licenses to all source files
diff --git a/verilog/gl/DFFRAM.v b/verilog/gl/DFFRAM.v
index 849fa90..bc350da 100644
--- a/verilog/gl/DFFRAM.v
+++ b/verilog/gl/DFFRAM.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module DFFRAM(CLK, EN, VPWR, VGND, A, Di, Do, WE);
diff --git a/verilog/gl/caravel.v b/verilog/gl/caravel.v
index 6319bdd..c68e423 100644
--- a/verilog/gl/caravel.v
+++ b/verilog/gl/caravel.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module caravel(vddio, vssio, vdda, vssa, vccd, vssd, vdda1, vdda2, vssa1, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, mprj_io, pwr_ctrl_out, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1);
diff --git a/verilog/gl/chip_io.v b/verilog/gl/chip_io.v
index 9fcb5ac..9c6bb4a 100644
--- a/verilog/gl/chip_io.v
+++ b/verilog/gl/chip_io.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module chip_io(vddio, vssio, vccd, vssd, vdda, vssa, vdda1, vdda2, vssa1, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1, porb_h, por, resetb_core_h, clock_core, gpio_out_core, gpio_in_core, gpio_mode0_core, gpio_mode1_core, gpio_outenb_core, gpio_inenb_core, flash_csb_core, flash_clk_core, flash_csb_oeb_core, flash_clk_oeb_core, flash_io0_oeb_core, flash_io1_oeb_core, flash_csb_ieb_core, flash_clk_ieb_core, flash_io0_ieb_core, flash_io1_ieb_core, flash_io0_do_core, flash_io1_do_core, flash_io0_di_core, flash_io1_di_core, mprj_io, mprj_io_out, mprj_io_oeb, mprj_io_hldh_n, mprj_io_enh, mprj_io_inp_dis, mprj_io_ib_mode_sel, mprj_io_vtrip_sel, mprj_io_slow_sel, mprj_io_holdover, mprj_io_analog_en, mprj_io_analog_sel, mprj_io_analog_pol, mprj_io_dm, mprj_io_in, mprj_analog_io);
diff --git a/verilog/gl/digital_pll.v b/verilog/gl/digital_pll.v
index 5e2d1f3..001afab 100644
--- a/verilog/gl/digital_pll.v
+++ b/verilog/gl/digital_pll.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module digital_pll(dco, enable, osc, resetb, VPWR, VGND, clockp, div, ext_trim);
diff --git a/verilog/gl/gpio_control_block.v b/verilog/gl/gpio_control_block.v
index 30ac390..7ef8381 100644
--- a/verilog/gl/gpio_control_block.v
+++ b/verilog/gl/gpio_control_block.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module gpio_control_block(mgmt_gpio_in, mgmt_gpio_oeb, mgmt_gpio_out, pad_gpio_ana_en, pad_gpio_ana_pol, pad_gpio_ana_sel, pad_gpio_holdover, pad_gpio_ib_mode_sel, pad_gpio_in, pad_gpio_inenb, pad_gpio_out, pad_gpio_outenb, pad_gpio_slow_sel, pad_gpio_vtrip_sel, resetn, serial_clock, serial_data_in, serial_data_out, user_gpio_in, user_gpio_oeb, user_gpio_out, VPWR, VGND, pad_gpio_dm);
diff --git a/verilog/gl/mgmt_core.v b/verilog/gl/mgmt_core.v
index 3cc7f78..17ce650 100644
--- a/verilog/gl/mgmt_core.v
+++ b/verilog/gl/mgmt_core.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module mgmt_core(clock, core_clk, core_rstn, flash_clk, flash_clk_ieb, flash_clk_oeb, flash_csb, flash_csb_ieb, flash_csb_oeb, flash_io0_di, flash_io0_do, flash_io0_ieb, flash_io0_oeb, flash_io1_di, flash_io1_do, flash_io1_ieb, flash_io1_oeb, gpio_in_pad, gpio_inenb_pad, gpio_mode0_pad, gpio_mode1_pad, gpio_out_pad, gpio_outenb_pad, jtag_out, jtag_outenb, mgmt_ena_ro, mprj2_vcc_pwrgood, mprj2_vdd_pwrgood, mprj_ack_i, mprj_cyc_o, mprj_io_loader_clock, mprj_io_loader_data, mprj_io_loader_resetn, mprj_stb_o, mprj_vcc_pwrgood, mprj_vdd_pwrgood, mprj_we_o, porb, resetb, sdo_out, sdo_outenb, user_clk, VPWR, VGND, la_input, la_oen, la_output, mask_rev, mgmt_addr, mgmt_addr_ro, mgmt_ena, mgmt_in_data, mgmt_out_data, mgmt_rdata, mgmt_rdata_ro, mgmt_wdata, mgmt_wen, mgmt_wen_mask, mprj_adr_o, mprj_dat_i, mprj_dat_o, mprj_sel_o, pwr_ctrl_out);
diff --git a/verilog/gl/mgmt_protect.v b/verilog/gl/mgmt_protect.v
index f1efcea..40d5357 100644
--- a/verilog/gl/mgmt_protect.v
+++ b/verilog/gl/mgmt_protect.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module mgmt_protect(caravel_clk, caravel_clk2, caravel_rstn, mprj_cyc_o_core, mprj_cyc_o_user, mprj_stb_o_core, mprj_stb_o_user, mprj_we_o_core, mprj_we_o_user, user1_vcc_powergood, user1_vdd_powergood, user2_vcc_powergood, user2_vdd_powergood, user_clock, user_clock2, user_reset, user_resetn, VPWR, VGND, la_data_in_core, la_data_in_mprj, la_data_out_core, la_data_out_mprj, la_oen_core, la_oen_mprj, mprj_adr_o_core, mprj_adr_o_user, mprj_dat_o_core, mprj_dat_o_user, mprj_sel_o_core, mprj_sel_o_user);
diff --git a/verilog/gl/mgmt_protect_hv.v b/verilog/gl/mgmt_protect_hv.v
index 22aa5c2..68a4634 100644
--- a/verilog/gl/mgmt_protect_hv.v
+++ b/verilog/gl/mgmt_protect_hv.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module mgmt_protect_hv(mprj2_vdd_logic1, mprj_vdd_logic1, VPWR, VGND);
diff --git a/verilog/gl/simple_por.v b/verilog/gl/simple_por.v
index 2291444..ce4133b 100644
--- a/verilog/gl/simple_por.v
+++ b/verilog/gl/simple_por.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
diff --git a/verilog/gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v b/verilog/gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
index 856b665..7dbac90 100644
--- a/verilog/gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
+++ b/verilog/gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped(A, X, VPWR, VGND);
diff --git a/verilog/gl/storage.v b/verilog/gl/storage.v
index a629e82..5c4fe5f 100644
--- a/verilog/gl/storage.v
+++ b/verilog/gl/storage.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
diff --git a/verilog/gl/user_id_programming.v b/verilog/gl/user_id_programming.v
index 25f9057..78dbd63 100644
--- a/verilog/gl/user_id_programming.v
+++ b/verilog/gl/user_id_programming.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module user_id_programming(VPWR, VGND, mask_rev);
diff --git a/verilog/gl/user_proj_example.v b/verilog/gl/user_proj_example.v
index c24b3f2..8267ec2 100644
--- a/verilog/gl/user_proj_example.v
+++ b/verilog/gl/user_proj_example.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module user_proj_example(wb_clk_i, wb_rst_i, wbs_ack_o, wbs_cyc_i, wbs_stb_i, wbs_we_i, VPWR, VGND, io_in, io_oeb, io_out, la_data_in, la_data_out, la_oen, wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i);
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index b4f15fa..8fda509 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -1,3 +1,17 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
/* Generated by Yosys 0.9+2406 (git sha1 347dd01, gcc 8.3.1 -fPIC -Os) */
module user_project_wrapper(user_clock2, vccd1, vccd2, vdda1, vdda2, vssa1, vssa2, vssd1, vssd2, wb_clk_i, wb_rst_i, wbs_ack_o, wbs_cyc_i, wbs_stb_i, wbs_we_i, VPWR, VGND, io_in, io_oeb, io_out, la_data_in, la_data_out, la_oen, wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i);
