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Tim Edwards581068f2020-11-19 12:45:25 -05001// `default_nettype none
agorararmard6c766a82020-12-10 18:13:12 +02002// SPDX-FileCopyrightText: 2020 Efabless Corporation
3//
4// Licensed under the Apache License, Version 2.0 (the "License");
5// you may not use this file except in compliance with the License.
6// You may obtain a copy of the License at
7//
8// http://www.apache.org/licenses/LICENSE-2.0
9//
10// Unless required by applicable law or agreed to in writing, software
11// distributed under the License is distributed on an "AS IS" BASIS,
12// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13// See the License for the specific language governing permissions and
14// limitations under the License.
15// SPDX-License-Identifier: Apache-2.0
Tim Edwardsef8312e2020-09-22 17:20:06 -040016/*--------------------------------------------------------------*/
17/* caravel, a project harness for the Google/SkyWater sky130 */
18/* fabrication process and open source PDK */
19/* */
20/* Copyright 2020 efabless, Inc. */
21/* Written by Tim Edwards, December 2019 */
22/* and Mohamed Shalan, August 2020 */
23/* This file is open source hardware released under the */
24/* Apache 2.0 license. See file LICENSE. */
25/* */
26/*--------------------------------------------------------------*/
27
Tim Edwardsef8312e2020-09-22 17:20:06 -040028module caravel (
Tim Edwards9eda80d2020-10-08 21:36:44 -040029 inout vddio, // Common 3.3V padframe/ESD power
30 inout vssio, // Common padframe/ESD ground
31 inout vdda, // Management 3.3V power
32 inout vssa, // Common analog ground
33 inout vccd, // Management/Common 1.8V power
34 inout vssd, // Common digital ground
35 inout vdda1, // User area 1 3.3V power
36 inout vdda2, // User area 2 3.3V power
37 inout vssa1, // User area 1 analog ground
38 inout vssa2, // User area 2 analog ground
39 inout vccd1, // User area 1 1.8V power
40 inout vccd2, // User area 2 1.8V power
41 inout vssd1, // User area 1 digital ground
42 inout vssd2, // User area 2 digital ground
43
Tim Edwards04ba17f2020-10-02 22:27:50 -040044 inout gpio, // Used for external LDO control
Tim Edwardsef8312e2020-09-22 17:20:06 -040045 inout [`MPRJ_IO_PADS-1:0] mprj_io,
Tim Edwardsba328902020-10-27 15:03:22 -040046 output [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
Tim Edwardsef8312e2020-09-22 17:20:06 -040047 input clock, // CMOS core clock input, not a crystal
Tim Edwards04ba17f2020-10-02 22:27:50 -040048 input resetb,
49
50 // Note that only two pins are available on the flash so dual and
51 // quad flash modes are not available.
52
Tim Edwardsef8312e2020-09-22 17:20:06 -040053 output flash_csb,
54 output flash_clk,
55 output flash_io0,
Tim Edwards04ba17f2020-10-02 22:27:50 -040056 output flash_io1
Tim Edwardsef8312e2020-09-22 17:20:06 -040057);
58
Tim Edwards04ba17f2020-10-02 22:27:50 -040059 //------------------------------------------------------------
60 // This value is uniquely defined for each user project.
61 //------------------------------------------------------------
Jeff DiCorpo62773de2021-02-19 00:38:25 -080062 parameter USER_PROJECT_ID = 32'h00010005;
Tim Edwardsef8312e2020-09-22 17:20:06 -040063
Tim Edwards04ba17f2020-10-02 22:27:50 -040064 // These pins are overlaid on mprj_io space. They have the function
65 // below when the management processor is in reset, or in the default
66 // configuration. They are assigned to uses in the user space by the
67 // configuration program running off of the SPI flash. Note that even
68 // when the user has taken control of these pins, they can be restored
69 // to the original use by setting the resetb pin low. The SPI pins and
70 // UART pins can be connected directly to an FTDI chip as long as the
71 // FTDI chip sets these lines to high impedence (input function) at
72 // all times except when holding the chip in reset.
73
74 // JTAG = mprj_io[0] (inout)
75 // SDO = mprj_io[1] (output)
76 // SDI = mprj_io[2] (input)
77 // CSB = mprj_io[3] (input)
78 // SCK = mprj_io[4] (input)
79 // ser_rx = mprj_io[5] (input)
80 // ser_tx = mprj_io[6] (output)
81 // irq = mprj_io[7] (input)
82
83 // These pins are reserved for any project that wants to incorporate
84 // its own processor and flash controller. While a user project can
85 // technically use any available I/O pins for the purpose, these
86 // four pins connect to a pass-through mode from the SPI slave (pins
87 // 1-4 above) so that any SPI flash connected to these specific pins
88 // can be accessed through the SPI slave even when the processor is in
89 // reset.
90
Tim Edwards44bab472020-10-04 22:09:54 -040091 // user_flash_csb = mprj_io[8]
92 // user_flash_sck = mprj_io[9]
93 // user_flash_io0 = mprj_io[10]
94 // user_flash_io1 = mprj_io[11]
Tim Edwards04ba17f2020-10-02 22:27:50 -040095
96 // One-bit GPIO dedicated to management SoC (outside of user control)
97 wire gpio_out_core;
98 wire gpio_in_core;
99 wire gpio_mode0_core;
100 wire gpio_mode1_core;
101 wire gpio_outenb_core;
102 wire gpio_inenb_core;
103
Tim Edwards6d9739d2020-10-19 11:00:49 -0400104 // User Project Control (pad-facing)
Tim Edwards04ba17f2020-10-02 22:27:50 -0400105 wire mprj_io_loader_resetn;
106 wire mprj_io_loader_clock;
107 wire mprj_io_loader_data;
108
Tim Edwardsef8312e2020-09-22 17:20:06 -0400109 wire [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n;
110 wire [`MPRJ_IO_PADS-1:0] mprj_io_enh;
111 wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
Tim Edwards44bab472020-10-04 22:09:54 -0400112 wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
Tim Edwardsef8312e2020-09-22 17:20:06 -0400113 wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400114 wire [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
115 wire [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
116 wire [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
Tim Edwardsef8312e2020-09-22 17:20:06 -0400117 wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
118 wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
119 wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
120 wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
121 wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
122 wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
123
Tim Edwards6d9739d2020-10-19 11:00:49 -0400124 // User Project Control (user-facing)
Tim Edwards44bab472020-10-04 22:09:54 -0400125 wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400126 wire [`MPRJ_IO_PADS-1:0] user_io_in;
127 wire [`MPRJ_IO_PADS-1:0] user_io_out;
Tim Edwards581068f2020-11-19 12:45:25 -0500128 wire [`MPRJ_IO_PADS-8:0] user_analog_io;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400129
130 /* Padframe control signals */
131 wire [`MPRJ_IO_PADS-1:0] gpio_serial_link;
132 wire mgmt_serial_clock;
133 wire mgmt_serial_resetn;
134
Tim Edwards6d9739d2020-10-19 11:00:49 -0400135 // User Project Control management I/O
Tim Edwards44bab472020-10-04 22:09:54 -0400136 // There are two types of GPIO connections:
137 // (1) Full Bidirectional: Management connects to in, out, and oeb
138 // Uses: JTAG and SDO
139 // (2) Selectable bidirectional: Management connects to in and out,
140 // which are tied together. oeb is grounded (oeb from the
141 // configuration is used)
142
143 // SDI = mprj_io[2] (input)
144 // CSB = mprj_io[3] (input)
145 // SCK = mprj_io[4] (input)
146 // ser_rx = mprj_io[5] (input)
147 // ser_tx = mprj_io[6] (output)
148 // irq = mprj_io[7] (input)
149
150 wire [`MPRJ_IO_PADS-1:0] mgmt_io_in;
Ahmed Ghazydf4dd882020-11-25 18:38:42 +0200151 wire jtag_out, sdo_out;
152 wire jtag_outenb, sdo_outenb;
Tim Edwards44bab472020-10-04 22:09:54 -0400153
154 wire [`MPRJ_IO_PADS-3:0] mgmt_io_nc1; /* no-connects */
155 wire [`MPRJ_IO_PADS-3:0] mgmt_io_nc3; /* no-connects */
156 wire [1:0] mgmt_io_nc2; /* no-connects */
157
Tim Edwards581068f2020-11-19 12:45:25 -0500158 wire clock_core;
159
Tim Edwards04ba17f2020-10-02 22:27:50 -0400160 // Power-on-reset signal. The reset pad generates the sense-inverted
161 // reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
162 // derived.
163
Tim Edwardsef8312e2020-09-22 17:20:06 -0400164 wire porb_h;
165 wire porb_l;
Tim Edwards581068f2020-11-19 12:45:25 -0500166 wire por_l;
Tim Edwardsef8312e2020-09-22 17:20:06 -0400167
Tim Edwardsf51dd082020-10-05 16:30:24 -0400168 wire rstb_h;
169 wire rstb_l;
170
Tim Edwards581068f2020-11-19 12:45:25 -0500171 wire flash_clk_core, flash_csb_core;
172 wire flash_clk_oeb_core, flash_csb_oeb_core;
173 wire flash_clk_ieb_core, flash_csb_ieb_core;
174 wire flash_io0_oeb_core, flash_io1_oeb_core;
175 wire flash_io2_oeb_core, flash_io3_oeb_core;
176 wire flash_io0_ieb_core, flash_io1_ieb_core;
177 wire flash_io2_ieb_core, flash_io3_ieb_core;
178 wire flash_io0_do_core, flash_io1_do_core;
179 wire flash_io2_do_core, flash_io3_do_core;
180 wire flash_io0_di_core, flash_io1_di_core;
181 wire flash_io2_di_core, flash_io3_di_core;
182
Tim Edwards44bab472020-10-04 22:09:54 -0400183 // To be considered: Master hold signal on all user pads (?)
184 // For now, set holdh_n to 1 (NOTE: This is in the 3.3V domain)
185 // and setting enh to porb_h.
Tim Edwards9eda80d2020-10-08 21:36:44 -0400186 assign mprj_io_hldh_n = {`MPRJ_IO_PADS{vddio}};
Tim Edwards44bab472020-10-04 22:09:54 -0400187 assign mprj_io_enh = {`MPRJ_IO_PADS{porb_h}};
188
Tim Edwardsef8312e2020-09-22 17:20:06 -0400189 chip_io padframe(
190 // Package Pins
Tim Edwards9eda80d2020-10-08 21:36:44 -0400191 .vddio(vddio),
192 .vssio(vssio),
193 .vdda(vdda),
194 .vssa(vssa),
195 .vccd(vccd),
196 .vssd(vssd),
197 .vdda1(vdda1),
198 .vdda2(vdda2),
199 .vssa1(vssa1),
200 .vssa2(vssa2),
201 .vccd1(vccd1),
202 .vccd2(vccd2),
203 .vssd1(vssd1),
204 .vssd2(vssd2),
205
Tim Edwardsef8312e2020-09-22 17:20:06 -0400206 .gpio(gpio),
207 .mprj_io(mprj_io),
208 .clock(clock),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400209 .resetb(resetb),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400210 .flash_csb(flash_csb),
211 .flash_clk(flash_clk),
212 .flash_io0(flash_io0),
213 .flash_io1(flash_io1),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400214 // SoC Core Interface
Tim Edwardsef8312e2020-09-22 17:20:06 -0400215 .porb_h(porb_h),
Tim Edwards581068f2020-11-19 12:45:25 -0500216 .por(por_l),
Tim Edwardsf51dd082020-10-05 16:30:24 -0400217 .resetb_core_h(rstb_h),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400218 .clock_core(clock_core),
219 .gpio_out_core(gpio_out_core),
220 .gpio_in_core(gpio_in_core),
221 .gpio_mode0_core(gpio_mode0_core),
222 .gpio_mode1_core(gpio_mode1_core),
223 .gpio_outenb_core(gpio_outenb_core),
224 .gpio_inenb_core(gpio_inenb_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400225 .flash_csb_core(flash_csb_core),
226 .flash_clk_core(flash_clk_core),
227 .flash_csb_oeb_core(flash_csb_oeb_core),
228 .flash_clk_oeb_core(flash_clk_oeb_core),
229 .flash_io0_oeb_core(flash_io0_oeb_core),
230 .flash_io1_oeb_core(flash_io1_oeb_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400231 .flash_csb_ieb_core(flash_csb_ieb_core),
232 .flash_clk_ieb_core(flash_clk_ieb_core),
233 .flash_io0_ieb_core(flash_io0_ieb_core),
234 .flash_io1_ieb_core(flash_io1_ieb_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400235 .flash_io0_do_core(flash_io0_do_core),
236 .flash_io1_do_core(flash_io1_do_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400237 .flash_io0_di_core(flash_io0_di_core),
238 .flash_io1_di_core(flash_io1_di_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400239 .mprj_io_in(mprj_io_in),
240 .mprj_io_out(mprj_io_out),
Tim Edwards44bab472020-10-04 22:09:54 -0400241 .mprj_io_oeb(mprj_io_oeb),
Manar14d35ac2020-10-21 22:47:15 +0200242 .mprj_io_hldh_n(mprj_io_hldh_n),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400243 .mprj_io_enh(mprj_io_enh),
Manar14d35ac2020-10-21 22:47:15 +0200244 .mprj_io_inp_dis(mprj_io_inp_dis),
245 .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
246 .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
247 .mprj_io_slow_sel(mprj_io_slow_sel),
248 .mprj_io_holdover(mprj_io_holdover),
249 .mprj_io_analog_en(mprj_io_analog_en),
250 .mprj_io_analog_sel(mprj_io_analog_sel),
251 .mprj_io_analog_pol(mprj_io_analog_pol),
Tim Edwards581068f2020-11-19 12:45:25 -0500252 .mprj_io_dm(mprj_io_dm),
253 .mprj_analog_io(user_analog_io)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400254 );
255
256 // SoC core
Tim Edwards04ba17f2020-10-02 22:27:50 -0400257 wire caravel_clk;
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400258 wire caravel_clk2;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400259 wire caravel_rstn;
Tim Edwardsef8312e2020-09-22 17:20:06 -0400260
261 wire [7:0] spi_ro_config_core;
262
263 // LA signals
Tim Edwards43e5c602020-11-19 15:59:50 -0500264 wire [127:0] la_data_in_user; // From CPU to MPRJ
265 wire [127:0] la_data_in_mprj; // From MPRJ to CPU
Tim Edwardsef8312e2020-09-22 17:20:06 -0400266 wire [127:0] la_data_out_mprj; // From CPU to MPRJ
Tim Edwards43e5c602020-11-19 15:59:50 -0500267 wire [127:0] la_data_out_user; // From MPRJ to CPU
268 wire [127:0] la_oen_user; // From CPU to MPRJ
269 wire [127:0] la_oen_mprj; // From CPU to MPRJ
270
Tim Edwards6d9739d2020-10-19 11:00:49 -0400271 // WB MI A (User Project)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400272 wire mprj_cyc_o_core;
273 wire mprj_stb_o_core;
274 wire mprj_we_o_core;
275 wire [3:0] mprj_sel_o_core;
276 wire [31:0] mprj_adr_o_core;
277 wire [31:0] mprj_dat_o_core;
278 wire mprj_ack_i_core;
279 wire [31:0] mprj_dat_i_core;
280
281 // WB MI B (xbar)
282 wire xbar_cyc_o_core;
283 wire xbar_stb_o_core;
284 wire xbar_we_o_core;
285 wire [3:0] xbar_sel_o_core;
286 wire [31:0] xbar_adr_o_core;
287 wire [31:0] xbar_dat_o_core;
288 wire xbar_ack_i_core;
289 wire [31:0] xbar_dat_i_core;
290
Tim Edwards04ba17f2020-10-02 22:27:50 -0400291 // Mask revision
292 wire [31:0] mask_rev;
293
Manar14d35ac2020-10-21 22:47:15 +0200294 wire mprj_clock;
295 wire mprj_clock2;
296 wire mprj_resetn;
Ahmed Ghazy69663c72020-11-18 20:15:53 +0200297 wire mprj_reset;
Manar14d35ac2020-10-21 22:47:15 +0200298 wire mprj_cyc_o_user;
299 wire mprj_stb_o_user;
300 wire mprj_we_o_user;
301 wire [3:0] mprj_sel_o_user;
302 wire [31:0] mprj_adr_o_user;
303 wire [31:0] mprj_dat_o_user;
304 wire mprj_vcc_pwrgood;
305 wire mprj2_vcc_pwrgood;
306 wire mprj_vdd_pwrgood;
307 wire mprj2_vdd_pwrgood;
308
Manar55ec3692020-10-30 16:32:18 +0200309 // Storage area
Ahmed Ghazydf4dd882020-11-25 18:38:42 +0200310 // Management R/W interface
311 wire [`RAM_BLOCKS-1:0] mgmt_ena;
Manarffe6cad2020-11-09 19:09:04 +0200312 wire [`RAM_BLOCKS-1:0] mgmt_wen;
313 wire [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask;
Manar55ec3692020-10-30 16:32:18 +0200314 wire [7:0] mgmt_addr;
315 wire [31:0] mgmt_wdata;
Manarffe6cad2020-11-09 19:09:04 +0200316 wire [(`RAM_BLOCKS*32)-1:0] mgmt_rdata;
Manar55ec3692020-10-30 16:32:18 +0200317 // Management RO interface
Ahmed Ghazydf4dd882020-11-25 18:38:42 +0200318 wire mgmt_ena_ro;
Manarffe6cad2020-11-09 19:09:04 +0200319 wire [7:0] mgmt_addr_ro;
320 wire [31:0] mgmt_rdata_ro;
Manar55ec3692020-10-30 16:32:18 +0200321
Ahmed Ghazy22d29d62020-10-28 03:42:02 +0200322 mgmt_core soc (
Manar61dce922020-11-10 19:26:28 +0200323 `ifdef USE_POWER_PINS
manarabdelatya115bdd2020-12-01 11:19:12 +0200324 .VPWR(vccd),
Jeff DiCorpo62773de2021-02-19 00:38:25 -0800325 .VGND(vssd),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400326 `endif
Tim Edwards04ba17f2020-10-02 22:27:50 -0400327 // GPIO (1 pin)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400328 .gpio_out_pad(gpio_out_core),
329 .gpio_in_pad(gpio_in_core),
330 .gpio_mode0_pad(gpio_mode0_core),
331 .gpio_mode1_pad(gpio_mode1_core),
332 .gpio_outenb_pad(gpio_outenb_core),
333 .gpio_inenb_pad(gpio_inenb_core),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400334 // Primary SPI flash controller
Tim Edwardsef8312e2020-09-22 17:20:06 -0400335 .flash_csb(flash_csb_core),
336 .flash_clk(flash_clk_core),
337 .flash_csb_oeb(flash_csb_oeb_core),
338 .flash_clk_oeb(flash_clk_oeb_core),
339 .flash_io0_oeb(flash_io0_oeb_core),
340 .flash_io1_oeb(flash_io1_oeb_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400341 .flash_csb_ieb(flash_csb_ieb_core),
342 .flash_clk_ieb(flash_clk_ieb_core),
343 .flash_io0_ieb(flash_io0_ieb_core),
344 .flash_io1_ieb(flash_io1_ieb_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400345 .flash_io0_do(flash_io0_do_core),
346 .flash_io1_do(flash_io1_do_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400347 .flash_io0_di(flash_io0_di_core),
348 .flash_io1_di(flash_io1_di_core),
Tim Edwardsf51dd082020-10-05 16:30:24 -0400349 // Master Reset
350 .resetb(rstb_l),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400351 .porb(porb_l),
352 // Clocks and reset
Tim Edwardsef8312e2020-09-22 17:20:06 -0400353 .clock(clock_core),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400354 .core_clk(caravel_clk),
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400355 .user_clk(caravel_clk2),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400356 .core_rstn(caravel_rstn),
Ahmed Ghazydf4dd882020-11-25 18:38:42 +0200357 // Logic Analyzer
Tim Edwards43e5c602020-11-19 15:59:50 -0500358 .la_input(la_data_in_mprj),
359 .la_output(la_data_out_mprj),
360 .la_oen(la_oen_mprj),
Tim Edwards6d9739d2020-10-19 11:00:49 -0400361 // User Project IO Control
Tim Edwards05ad4fc2020-10-19 22:12:33 -0400362 .mprj_vcc_pwrgood(mprj_vcc_pwrgood),
363 .mprj2_vcc_pwrgood(mprj2_vcc_pwrgood),
364 .mprj_vdd_pwrgood(mprj_vdd_pwrgood),
365 .mprj2_vdd_pwrgood(mprj2_vdd_pwrgood),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400366 .mprj_io_loader_resetn(mprj_io_loader_resetn),
367 .mprj_io_loader_clock(mprj_io_loader_clock),
368 .mprj_io_loader_data(mprj_io_loader_data),
Tim Edwards44bab472020-10-04 22:09:54 -0400369 .mgmt_in_data(mgmt_io_in),
Tim Edwardsca2f3182020-10-06 10:05:11 -0400370 .mgmt_out_data({mgmt_io_in[(`MPRJ_IO_PADS-1):2], mgmt_io_nc2}),
Tim Edwardsba328902020-10-27 15:03:22 -0400371 .pwr_ctrl_out(pwr_ctrl_out),
Tim Edwardsca2f3182020-10-06 10:05:11 -0400372 .sdo_out(sdo_out),
373 .sdo_outenb(sdo_outenb),
374 .jtag_out(jtag_out),
375 .jtag_outenb(jtag_outenb),
Tim Edwards6d9739d2020-10-19 11:00:49 -0400376 // User Project Slave ports (WB MI A)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400377 .mprj_cyc_o(mprj_cyc_o_core),
378 .mprj_stb_o(mprj_stb_o_core),
379 .mprj_we_o(mprj_we_o_core),
380 .mprj_sel_o(mprj_sel_o_core),
381 .mprj_adr_o(mprj_adr_o_core),
382 .mprj_dat_o(mprj_dat_o_core),
383 .mprj_ack_i(mprj_ack_i_core),
384 .mprj_dat_i(mprj_dat_i_core),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400385 // mask data
Manar55ec3692020-10-30 16:32:18 +0200386 .mask_rev(mask_rev),
Ahmed Ghazydf4dd882020-11-25 18:38:42 +0200387 // MGMT area R/W interface
388 .mgmt_ena(mgmt_ena),
Manar55ec3692020-10-30 16:32:18 +0200389 .mgmt_wen_mask(mgmt_wen_mask),
390 .mgmt_wen(mgmt_wen),
391 .mgmt_addr(mgmt_addr),
392 .mgmt_wdata(mgmt_wdata),
393 .mgmt_rdata(mgmt_rdata),
Manarffe6cad2020-11-09 19:09:04 +0200394 // MGMT area RO interface
395 .mgmt_ena_ro(mgmt_ena_ro),
396 .mgmt_addr_ro(mgmt_addr_ro),
397 .mgmt_rdata_ro(mgmt_rdata_ro)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400398 );
399
Tim Edwards53d92182020-10-11 21:47:40 -0400400 /* Clock and reset to user space are passed through a tristate */
401 /* buffer like the above, but since they are intended to be */
402 /* always active, connect the enable to the logic-1 output from */
403 /* the vccd1 domain. */
404
Tim Edwards53d92182020-10-11 21:47:40 -0400405 mgmt_protect mgmt_buffers (
Ahmed Ghazyfe9c3bb2020-11-26 15:29:48 +0200406 `ifdef USE_POWER_PINS
Tim Edwards53d92182020-10-11 21:47:40 -0400407 .vccd(vccd),
408 .vssd(vssd),
409 .vccd1(vccd1),
410 .vssd1(vssd1),
Tim Edwards05ad4fc2020-10-19 22:12:33 -0400411 .vdda1(vdda1),
412 .vssa1(vssa1),
413 .vdda2(vdda2),
414 .vssa2(vssa2),
Ahmed Ghazyfe9c3bb2020-11-26 15:29:48 +0200415 `endif
Tim Edwards21a9aac2020-10-12 22:05:18 -0400416
Tim Edwards53d92182020-10-11 21:47:40 -0400417 .caravel_clk(caravel_clk),
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400418 .caravel_clk2(caravel_clk2),
Tim Edwards53d92182020-10-11 21:47:40 -0400419 .caravel_rstn(caravel_rstn),
420 .mprj_cyc_o_core(mprj_cyc_o_core),
421 .mprj_stb_o_core(mprj_stb_o_core),
422 .mprj_we_o_core(mprj_we_o_core),
423 .mprj_sel_o_core(mprj_sel_o_core),
424 .mprj_adr_o_core(mprj_adr_o_core),
425 .mprj_dat_o_core(mprj_dat_o_core),
Tim Edwards43e5c602020-11-19 15:59:50 -0500426 .la_data_out_core(la_data_out_user),
427 .la_data_out_mprj(la_data_out_mprj),
428 .la_data_in_core(la_data_in_user),
429 .la_data_in_mprj(la_data_in_mprj),
430 .la_oen_mprj(la_oen_mprj),
431 .la_oen_core(la_oen_user),
Tim Edwards53d92182020-10-11 21:47:40 -0400432
433 .user_clock(mprj_clock),
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400434 .user_clock2(mprj_clock2),
Tim Edwards53d92182020-10-11 21:47:40 -0400435 .user_resetn(mprj_resetn),
Ahmed Ghazy69663c72020-11-18 20:15:53 +0200436 .user_reset(mprj_reset),
Tim Edwards53d92182020-10-11 21:47:40 -0400437 .mprj_cyc_o_user(mprj_cyc_o_user),
438 .mprj_stb_o_user(mprj_stb_o_user),
439 .mprj_we_o_user(mprj_we_o_user),
440 .mprj_sel_o_user(mprj_sel_o_user),
441 .mprj_adr_o_user(mprj_adr_o_user),
442 .mprj_dat_o_user(mprj_dat_o_user),
Tim Edwards05ad4fc2020-10-19 22:12:33 -0400443 .user1_vcc_powergood(mprj_vcc_pwrgood),
444 .user2_vcc_powergood(mprj2_vcc_pwrgood),
445 .user1_vdd_powergood(mprj_vdd_pwrgood),
446 .user2_vdd_powergood(mprj2_vdd_pwrgood)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400447 );
Tim Edwards53d92182020-10-11 21:47:40 -0400448
Ahmed Ghazydf4dd882020-11-25 18:38:42 +0200449
Tim Edwardsb86fc842020-10-13 17:11:54 -0400450 /*----------------------------------------------*/
451 /* Wrapper module around the user project */
452 /*----------------------------------------------*/
Tim Edwards05537512020-10-06 14:59:26 -0400453
Ahmed Ghazy22d29d62020-10-28 03:42:02 +0200454 user_project_wrapper mprj (
Ahmed Ghazyfe9c3bb2020-11-26 15:29:48 +0200455 `ifdef USE_POWER_PINS
Tim Edwards21a9aac2020-10-12 22:05:18 -0400456 .vdda1(vdda1), // User area 1 3.3V power
457 .vdda2(vdda2), // User area 2 3.3V power
458 .vssa1(vssa1), // User area 1 analog ground
459 .vssa2(vssa2), // User area 2 analog ground
460 .vccd1(vccd1), // User area 1 1.8V power
461 .vccd2(vccd2), // User area 2 1.8V power
462 .vssd1(vssd1), // User area 1 digital ground
463 .vssd2(vssd2), // User area 2 digital ground
Ahmed Ghazyfe9c3bb2020-11-26 15:29:48 +0200464 `endif
Tim Edwards21a9aac2020-10-12 22:05:18 -0400465
Tim Edwards53d92182020-10-11 21:47:40 -0400466 .wb_clk_i(mprj_clock),
Ahmed Ghazy69663c72020-11-18 20:15:53 +0200467 .wb_rst_i(mprj_reset),
Ahmed Ghazydf4dd882020-11-25 18:38:42 +0200468 // MGMT SoC Wishbone Slave
Tim Edwards53d92182020-10-11 21:47:40 -0400469 .wbs_cyc_i(mprj_cyc_o_user),
470 .wbs_stb_i(mprj_stb_o_user),
471 .wbs_we_i(mprj_we_o_user),
472 .wbs_sel_i(mprj_sel_o_user),
473 .wbs_adr_i(mprj_adr_o_user),
474 .wbs_dat_i(mprj_dat_o_user),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400475 .wbs_ack_o(mprj_ack_i_core),
476 .wbs_dat_o(mprj_dat_i_core),
477 // Logic Analyzer
Tim Edwards43e5c602020-11-19 15:59:50 -0500478 .la_data_in(la_data_in_user),
479 .la_data_out(la_data_out_user),
480 .la_oen(la_oen_user),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400481 // IO Pads
Tim Edwards05537512020-10-06 14:59:26 -0400482 .io_in (user_io_in),
Tim Edwardsef2b68d2020-10-11 17:00:44 -0400483 .io_out(user_io_out),
Tim Edwardsb86fc842020-10-13 17:11:54 -0400484 .io_oeb(user_io_oeb),
Tim Edwards581068f2020-11-19 12:45:25 -0500485 .analog_io(user_analog_io),
Tim Edwardsb86fc842020-10-13 17:11:54 -0400486 // Independent clock
487 .user_clock2(mprj_clock2)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400488 );
489
Tim Edwards05537512020-10-06 14:59:26 -0400490 /*--------------------------------------*/
491 /* End user project instantiation */
492 /*--------------------------------------*/
493
Tim Edwards04ba17f2020-10-02 22:27:50 -0400494 wire [`MPRJ_IO_PADS-1:0] gpio_serial_link_shifted;
495
Tim Edwards251e0df2020-10-05 11:02:12 -0400496 assign gpio_serial_link_shifted = {gpio_serial_link[`MPRJ_IO_PADS-2:0], mprj_io_loader_data};
Tim Edwards04ba17f2020-10-02 22:27:50 -0400497
Tim Edwards251e0df2020-10-05 11:02:12 -0400498 // Each control block sits next to an I/O pad in the user area.
499 // It gets input through a serial chain from the previous control
500 // block and passes it to the next control block. Due to the nature
501 // of the shift register, bits are presented in reverse, as the first
502 // bit in ends up as the last bit of the last I/O pad control block.
Tim Edwards44bab472020-10-04 22:09:54 -0400503
Tim Edwards89f09242020-10-05 15:17:34 -0400504 // There are two types of block; the first two are configured to be
505 // full bidirectional under control of the management Soc (JTAG and
506 // SDO). The rest are configured to be default (input).
507
Tim Edwards251e0df2020-10-05 11:02:12 -0400508 gpio_control_block #(
manarabdelaty589a5282020-12-05 01:06:48 +0200509 .DM_INIT(`DM_INIT), // Mode = output, strong up/down
510 .OENB_INIT(`OENB_INIT) // Enable output signaling from wire
Tim Edwards89f09242020-10-05 15:17:34 -0400511 ) gpio_control_bidir [1:0] (
Manar61dce922020-11-10 19:26:28 +0200512 `ifdef USE_POWER_PINS
Manar68e03632020-11-09 13:25:13 +0200513 .vccd(vccd),
514 .vssd(vssd),
515 .vccd1(vccd1),
516 .vssd1(vssd1),
Tim Edwards53d92182020-10-11 21:47:40 -0400517 `endif
Tim Edwards44bab472020-10-04 22:09:54 -0400518
Tim Edwards04ba17f2020-10-02 22:27:50 -0400519 // Management Soc-facing signals
520
Tim Edwardsc18c4742020-10-03 11:26:39 -0400521 .resetn(mprj_io_loader_resetn),
522 .serial_clock(mprj_io_loader_clock),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400523
Tim Edwards89f09242020-10-05 15:17:34 -0400524 .mgmt_gpio_in(mgmt_io_in[1:0]),
525 .mgmt_gpio_out({sdo_out, jtag_out}),
526 .mgmt_gpio_oeb({sdo_outenb, jtag_outenb}),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400527
Ahmed Ghazyd0dcdcf2020-12-15 22:00:25 +0200528 .one(),
529 .zero(),
530
Tim Edwards04ba17f2020-10-02 22:27:50 -0400531 // Serial data chain for pad configuration
Tim Edwards89f09242020-10-05 15:17:34 -0400532 .serial_data_in(gpio_serial_link_shifted[1:0]),
533 .serial_data_out(gpio_serial_link[1:0]),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400534
535 // User-facing signals
Tim Edwards89f09242020-10-05 15:17:34 -0400536 .user_gpio_out(user_io_out[1:0]),
537 .user_gpio_oeb(user_io_oeb[1:0]),
538 .user_gpio_in(user_io_in[1:0]),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400539
540 // Pad-facing signals (Pad GPIOv2)
Tim Edwards89f09242020-10-05 15:17:34 -0400541 .pad_gpio_inenb(mprj_io_inp_dis[1:0]),
542 .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
543 .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
544 .pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
545 .pad_gpio_holdover(mprj_io_holdover[1:0]),
546 .pad_gpio_ana_en(mprj_io_analog_en[1:0]),
547 .pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
548 .pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
549 .pad_gpio_dm(mprj_io_dm[5:0]),
550 .pad_gpio_outenb(mprj_io_oeb[1:0]),
551 .pad_gpio_out(mprj_io_out[1:0]),
552 .pad_gpio_in(mprj_io_in[1:0])
553 );
554
Ahmed Ghazyd0dcdcf2020-12-15 22:00:25 +0200555 wire [`MPRJ_IO_PADS-1:2] one_loop;
Tim Edwards89f09242020-10-05 15:17:34 -0400556 gpio_control_block gpio_control_in [`MPRJ_IO_PADS-1:2] (
Manar61dce922020-11-10 19:26:28 +0200557 `ifdef USE_POWER_PINS
Manar68e03632020-11-09 13:25:13 +0200558 .vccd(vccd),
559 .vssd(vssd),
560 .vccd1(vccd1),
561 .vssd1(vssd1),
Tim Edwards53d92182020-10-11 21:47:40 -0400562 `endif
Tim Edwards89f09242020-10-05 15:17:34 -0400563
564 // Management Soc-facing signals
565
566 .resetn(mprj_io_loader_resetn),
567 .serial_clock(mprj_io_loader_clock),
568
569 .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):2]),
570 .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-1):2]),
Ahmed Ghazyd0dcdcf2020-12-15 22:00:25 +0200571 .mgmt_gpio_oeb(one_loop),
572
573 .one(one_loop),
574 .zero(),
Tim Edwards89f09242020-10-05 15:17:34 -0400575
576 // Serial data chain for pad configuration
577 .serial_data_in(gpio_serial_link_shifted[(`MPRJ_IO_PADS-1):2]),
578 .serial_data_out(gpio_serial_link[(`MPRJ_IO_PADS-1):2]),
579
580 // User-facing signals
581 .user_gpio_out(user_io_out[(`MPRJ_IO_PADS-1):2]),
582 .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-1):2]),
583 .user_gpio_in(user_io_in[(`MPRJ_IO_PADS-1):2]),
584
585 // Pad-facing signals (Pad GPIOv2)
586 .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-1):2]),
587 .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-1):2]),
588 .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-1):2]),
589 .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-1):2]),
590 .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-1):2]),
591 .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-1):2]),
592 .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-1):2]),
593 .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-1):2]),
594 .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-1):6]),
595 .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-1):2]),
596 .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-1):2]),
597 .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):2])
Tim Edwards04ba17f2020-10-02 22:27:50 -0400598 );
599
Tim Edwards04ba17f2020-10-02 22:27:50 -0400600 user_id_programming #(
601 .USER_PROJECT_ID(USER_PROJECT_ID)
602 ) user_id_value (
Ahmed Ghazy27200e92020-11-25 22:07:02 +0200603`ifdef USE_POWER_PINS
manarabdelatyc7524312020-12-07 18:13:54 +0200604 .VPWR(vccd),
605 .VGND(vssd),
Ahmed Ghazy27200e92020-11-25 22:07:02 +0200606`endif
Tim Edwards04ba17f2020-10-02 22:27:50 -0400607 .mask_rev(mask_rev)
608 );
609
Tim Edwardsf51dd082020-10-05 16:30:24 -0400610 // Power-on-reset circuit
611 simple_por por (
Ahmed Ghazy27200e92020-11-25 22:07:02 +0200612`ifdef USE_POWER_PINS
Tim Edwards9eda80d2020-10-08 21:36:44 -0400613 .vdd3v3(vddio),
Tim Edwards581068f2020-11-19 12:45:25 -0500614 .vdd1v8(vccd),
Tim Edwards9eda80d2020-10-08 21:36:44 -0400615 .vss(vssio),
Ahmed Ghazy27200e92020-11-25 22:07:02 +0200616`endif
Tim Edwards581068f2020-11-19 12:45:25 -0500617 .porb_h(porb_h),
618 .porb_l(porb_l),
619 .por_l(por_l)
Tim Edwardsf51dd082020-10-05 16:30:24 -0400620 );
621
622 // XRES (chip input pin reset) reset level converter
Ahmed Ghazy1d1679d2020-11-30 17:44:45 +0200623 sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped rstb_level (
Ahmed Ghazy69663c72020-11-18 20:15:53 +0200624`ifdef USE_POWER_PINS
Tim Edwards21a9aac2020-10-12 22:05:18 -0400625 .VPWR(vddio),
Tim Edwards21a9aac2020-10-12 22:05:18 -0400626 .LVPWR(vccd),
Tim Edwards21a9aac2020-10-12 22:05:18 -0400627 .VGND(vssio),
Ahmed Ghazy69663c72020-11-18 20:15:53 +0200628`endif
Tim Edwardsf51dd082020-10-05 16:30:24 -0400629 .A(rstb_h),
630 .X(rstb_l)
631 );
632
Manar55ec3692020-10-30 16:32:18 +0200633 // Storage area
Manarffe6cad2020-11-09 19:09:04 +0200634 storage storage(
Manar55ec3692020-10-30 16:32:18 +0200635 .mgmt_clk(caravel_clk),
636 .mgmt_ena(mgmt_ena),
637 .mgmt_wen(mgmt_wen),
638 .mgmt_wen_mask(mgmt_wen_mask),
639 .mgmt_addr(mgmt_addr),
640 .mgmt_wdata(mgmt_wdata),
641 .mgmt_rdata(mgmt_rdata),
Ahmed Ghazydf4dd882020-11-25 18:38:42 +0200642 // Management RO interface
Manarffe6cad2020-11-09 19:09:04 +0200643 .mgmt_ena_ro(mgmt_ena_ro),
644 .mgmt_addr_ro(mgmt_addr_ro),
645 .mgmt_rdata_ro(mgmt_rdata_ro)
Manar55ec3692020-10-30 16:32:18 +0200646 );
647
Tim Edwardsef8312e2020-09-22 17:20:06 -0400648endmodule
Tim Edwards581068f2020-11-19 12:45:25 -0500649// `default_nettype wire