verilog/rtl/user_proj_example.sdc

create_clock [get_ports wb_clk_i]  -name wb_clk_i  -period 35
create_clock [get_ports user_clock2]  -name user_clock2  -period 100
set_clock_groups -asynchronous \
   -group [get_clocks {wb_clk_i}] \
   -group [get_clocks {user_clock2}]

#set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
#set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
#puts "\[INFO\]: Setting output delay to: $output_delay_value"
#puts "\[INFO\]: Setting input delay to: $input_delay_value"


#set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
##set rst_indx [lsearch [all_inputs] [get_port resetn]]
#set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
##set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
#set all_inputs_wo_clk_rst $all_inputs_wo_clk


# correct resetn
#set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
#set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]

# TODO set this as parameter
#set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
#set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
#puts "\[INFO\]: Setting load to: $cap_load"
#set_load  $cap_load [all_outputs]