| // Copyright 2020 Efabless Corporation |
| // |
| // Licensed under the Apache License, Version 2.0 (the "License"); |
| // you may not use this file except in compliance with the License. |
| // You may obtain a copy of the License at |
| // |
| // http://www.apache.org/licenses/LICENSE-2.0 |
| // |
| // Unless required by applicable law or agreed to in writing, software |
| // distributed under the License is distributed on an "AS IS" BASIS, |
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| // See the License for the specific language governing permissions and |
| // limitations under the License. |
| // SPDX-License-Identifier: Apache-2.0 |
| |
| /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */ |
| |
| module mgmt_protect_hv(mprj2_vdd_logic1, mprj_vdd_logic1, VPWR, VGND); |
| input VGND; |
| input VPWR; |
| output mprj2_vdd_logic1; |
| wire mprj2_vdd_logic1_h; |
| output mprj_vdd_logic1; |
| wire mprj_vdd_logic1_h; |
| sky130_fd_sc_hvl__decap_8 FILLER_0_0 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_8 FILLER_0_16 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_8 FILLER_0_24 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_8 FILLER_0_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_8 FILLER_0_40 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__fill_2 FILLER_0_48 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_8 FILLER_0_8 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__fill_2 FILLER_1_48 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_4 FILLER_1_5 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_8 FILLER_2_0 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_4 FILLER_2_43 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__fill_2 FILLER_2_47 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__fill_1 FILLER_2_49 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__fill_1 FILLER_2_8 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_8 FILLER_3_0 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_8 FILLER_3_16 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_8 FILLER_3_24 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_8 FILLER_3_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_8 FILLER_3_40 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__fill_2 FILLER_3_48 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__decap_8 FILLER_3_8 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__conb_1 mprj2_logic_high_hvl ( |
| .HI(mprj2_vdd_logic1_h), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__lsbufhv2lv_1 mprj2_logic_high_lv ( |
| .A(mprj2_vdd_logic1_h), |
| .LVPWR(VPWR), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(mprj2_vdd_logic1) |
| ); |
| sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl ( |
| .HI(mprj_vdd_logic1_h), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hvl__lsbufhv2lv_1 mprj_logic_high_lv ( |
| .A(mprj_vdd_logic1_h), |
| .LVPWR(VPWR), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(mprj_vdd_logic1) |
| ); |
| endmodule |