Add missing USE_POWER_PINS in other modules

verilog/rtl/gpio_control_block.v

diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index ed3d531..f9764ed 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -209,19 +209,23 @@
     /* Buffer user_gpio_in with an enable that is set by the user domain vccd */
 
     sky130_fd_sc_hd__conb_1 gpio_logic_high (
+`ifdef USE_POWER_PINS
             .VPWR(vccd1),
             .VGND(vssd1),
             .VPB(vccd1),
             .VNB(vssd1),
+`endif
             .HI(gpio_logic1),
             .LO()
     );
 
     sky130_fd_sc_hd__einvp_8 gpio_in_buf (
+`ifdef USE_POWER_PINS
             .VPWR(vccd),
             .VGND(vssd),
             .VPB(vccd),
             .VNB(vssd),
+`endif
             .Z(user_gpio_in),
             .A(~gpio_in_unbuf),
             .TE(gpio_logic1)

verilog/rtl/user_id_programming.v

diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index d3186c1..421e663 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -18,10 +18,12 @@
     // For the mask revision input, use an array of digital constant logic cells
 
     sky130_fd_sc_hd__conb_1 mask_rev_value [31:0] (
+`ifdef USE_POWER_PINS
             .VPWR(vdd1v8),
             .VPB(vdd1v8),
             .VNB(vss),
             .VGND(vss),
+`endif
             .HI(user_proj_id_high),
             .LO(user_proj_id_low)
     );