Wrap lsbufhv2lv to eliminate li1 pins at the top

verilog/rtl/caravel.v

diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 23851dd..bd3a167 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -49,6 +49,7 @@
 `include "DFFRAMBB.v"
 `include "sram_1rw1r_32_256_8_sky130.v"
 `include "storage.v"
+`include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
 
 /*------------------------------*/
 /* Include user project here	*/
@@ -647,7 +648,7 @@
     );
 
     // XRES (chip input pin reset) reset level converter
-    sky130_fd_sc_hvl__lsbufhv2lv_1 rstb_level (
+    sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped rstb_level (
 `ifdef USE_POWER_PINS
 		.VPWR(vddio),
 		.VPB(vddio),

verilog/rtl/mgmt_protect_hv.v

diff --git a/verilog/rtl/mgmt_protect_hv.v b/verilog/rtl/mgmt_protect_hv.v
index 9c8cabe..dbd04bb 100644
--- a/verilog/rtl/mgmt_protect_hv.v
+++ b/verilog/rtl/mgmt_protect_hv.v
@@ -10,12 +10,14 @@
 /*----------------------------------------------------------------------*/
 
 module mgmt_protect_hv (
+`ifdef USE_POWER_PINS
     inout	vccd,
     inout	vssd,
     inout	vdda1,
     inout	vssa1,
     inout	vdda2,
     inout	vssa2,
+`endif
 
     output	mprj_vdd_logic1,
     output	mprj2_vdd_logic1

verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v

diff --git a/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v b/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
new file mode 100644
index 0000000..f992c1e
--- /dev/null
+++ b/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
@@ -0,0 +1,35 @@
+module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped (
+	X    ,
+	A    ,
+`ifdef USE_POWER_PINS
+	VPWR ,
+	VGND ,
+	LVPWR,
+	VPB  ,
+	VNB
+`endif
+);
+
+output X    ;
+input  A    ;
+`ifdef USE_POWER_PINS
+input  VPWR ;
+input  VGND ;
+input  LVPWR;
+input  VPB  ;
+input  VNB  ;
+`endif
+
+sky130_fd_sc_hvl__lsbufhv2lv_1 lvlshiftdown (
+`ifdef USE_POWER_PINS
+	.VPWR(VPWR),
+	.VPB(VPB),
+	.LVPWR(LVPWR),
+	.VNB(VNB),
+	.VGND(VGND),
+`endif
+	.A(A),
+	.X(X)
+);
+
+endmodule