blob: 22cba29057556d5deb10da36970f3b84a47b51f0 [file] [log] [blame]
Bryce-Readyhough125ff3b2020-12-07 09:55:39 -08001* NGSPICE file created from diff-amp.ext - technology: sky130A
2
3* Include SkyWater sky130 device models
4.include "/home/mhasan13/pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/r+c/res_typical__cap_typical__lin.spice"
5.include "/home/mhasan13/pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/r+c/res_typical__cap_typical.spice"
6.include "/home/mhasan13/pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/tt.spice"
7
8* Vdd vdd gnd DC 0.7
9* Vgnd vss gnd DC 0.0
10* Ibias vdd i_bias DC 1n
11* Vref in_2 vout DC 0.0
12* Vin in_1 gnd DC 0.2
13
14Vdd vdd gnd DC 0.7
15Vgnd vss gnd DC 0.0
16Ibias vdd i_bias DC 1n
17Vshort in_2 vout DC 0.0
18Vin in_1 gnd DC PULSE(0 0.7 100p 1u 1u 10u 20u)
19
20.subckt sky130_fd_pr__pfet_01v8_hymyl3 VSUBS a_n50_n112# a_50_n86# w_n144_n148# a_n108_n86#
21X0 a_50_n86# a_n50_n112# a_n108_n86# w_n144_n148# sky130_fd_pr__pfet_01v8 w=500000u l=500000u
22.ends
23
24.subckt sky130_fd_pr__nfet_01v8_2qpbu2 VSUBS a_n108_n131# a_n50_n157# a_50_n131#
25X0 a_50_n131# a_n50_n157# a_n108_n131# VSUBS sky130_fd_pr__nfet_01v8 w=1e+06u l=500000u
26.ends
27
28.subckt sky130_fd_pr__nfet_01v8_hhwku0 VSUBS a_n50_n107# a_50_n81# a_n108_n81#
29X0 a_50_n81# a_n50_n107# a_n108_n81# VSUBS sky130_fd_pr__nfet_01v8 w=500000u l=500000u
30.ends
31
32.subckt diff-amp in_1 in_2 i_bias vdd vss vout
33Xsky130_fd_pr__pfet_01v8_hymyl3_0 vss li_92_184# li_92_184# vdd vdd sky130_fd_pr__pfet_01v8_hymyl3
34Xsky130_fd_pr__pfet_01v8_hymyl3_1 vss li_92_184# vdd vdd vout sky130_fd_pr__pfet_01v8_hymyl3
35Xsky130_fd_pr__nfet_01v8_2qpbu2_0 vss vss i_bias li_176_12# sky130_fd_pr__nfet_01v8_2qpbu2
36Xsky130_fd_pr__nfet_01v8_2qpbu2_1 vss i_bias i_bias vss sky130_fd_pr__nfet_01v8_2qpbu2
37Xsky130_fd_pr__nfet_01v8_hhwku0_0 vss in_1 li_92_184# li_176_12# sky130_fd_pr__nfet_01v8_hhwku0
38Xsky130_fd_pr__nfet_01v8_hhwku0_1 vss in_2 li_176_12# vout sky130_fd_pr__nfet_01v8_hhwku0
39.ends
40
41
42
43*instantiate
44Xdiff in_1 in_2 i_bias vdd vss vout diff-amp
45
46.control
47* dc Vin 0 0.7 0.01
48* plot v(in_2) v(in_1) v(vout)
49
50tran 100n 50u
51plot v(in_1) v(vout)
52.endc
53.end