openlane/user_id_programming/runs/user_id_programming/logs/lvs/write_powered_verilog.log

Notice 0: Reading LEF file:  /project/openlane/user_id_programming/runs/user_id_programming/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/user_id_programming/runs/user_id_programming/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_id_programming/runs/user_id_programming/results/routing/user_id_programming.def
Notice 0: Design: user_id_programming
Notice 0:     Created 36 pins.
Notice 0:     Created 112 components and 502 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 66 nets and 64 connections.
Notice 0: Finished DEF file: /project/openlane/user_id_programming/runs/user_id_programming/results/routing/user_id_programming.def
Top-level design name: user_id_programming
Found port VPWR of type SIGNAL
Found port VGND of type SIGNAL
Power net:  VPWR
Ground net: VGND
Modified power connections of 112 cells (Remaining: 0 ).