commit 442825e5699c17e4c4490673fd6709451cc233ce
author Ahmed Ghazy <ax3ghazy@aucegypt.edu> Mon Dec 14 19:12:34 2020 +0200
committer Ahmed Ghazy <ax3ghazy@aucegypt.edu> Mon Dec 14 19:12:34 2020 +0200
tree 1fb782e461b5f791401ef8090d9a65d7ca068820
parent 94dabb8582f4760d43d328fb676ba74dcfa1c08c

Refactor mgmt_protect.v into separate islands

verilog/rtl/caravel.v

diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 430b2f5..d58aa9b 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -70,6 +70,8 @@
 	`include "chip_io.v"
 `endif
 
+`include "mprj_logic_high.v"
+`include "mprj2_logic_high.v"
 `include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
 `include "mgmt_protect.v"
 `include "mgmt_protect_hv.v"

verilog/rtl/mgmt_protect.v

diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index 25e0b8e..5220bce 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -95,26 +95,20 @@
 
 	wire [127:0] la_data_in_mprj_bar;
 
-        sky130_fd_sc_hd__conb_1 mprj_logic_high [458:0] (
+        mprj_logic_high mprj_logic_high_inst (
 `ifdef USE_POWER_PINS
-                .VPWR(vccd1),
-                .VGND(vssd1),
-                .VPB(vccd1),
-                .VNB(vssd1),
+                .vccd1(vccd1),
+                .vssd1(vssd1),
 `endif
-                .HI(mprj_logic1),
-                .LO()
+                .HI(mprj_logic1)
         );
 
-        sky130_fd_sc_hd__conb_1 mprj2_logic_high (
+        mprj2_logic_high mprj2_logic_high_inst (
 `ifdef USE_POWER_PINS
-                .VPWR(vccd2),
-                .VGND(vssd2),
-                .VPB(vccd2),
-                .VNB(vssd2),
+                .vccd2(vccd2),
+                .vssd2(vssd2),
 `endif
-                .HI(mprj2_logic1),
-                .LO()
+                .HI(mprj2_logic1)
         );
 
 	// Logic high in the VDDA (3.3V) domains

verilog/rtl/mprj2_logic_high.v

diff --git a/verilog/rtl/mprj2_logic_high.v b/verilog/rtl/mprj2_logic_high.v
new file mode 100644
index 0000000..f57f173
--- /dev/null
+++ b/verilog/rtl/mprj2_logic_high.v
@@ -0,0 +1,18 @@
+module mprj2_logic_high (
+`ifdef USE_POWER_PINS
+    inout	   vccd2,
+    inout	   vssd2,
+`endif
+    output         HI
+);
+sky130_fd_sc_hd__conb_1 inst (
+`ifdef USE_POWER_PINS
+                .VPWR(vccd2),
+                .VGND(vssd2),
+                .VPB(vccd2),
+                .VNB(vssd2),
+`endif
+                .HI(HI),
+                .LO()
+        );
+endmodule

verilog/rtl/mprj_logic_high.v

diff --git a/verilog/rtl/mprj_logic_high.v b/verilog/rtl/mprj_logic_high.v
new file mode 100644
index 0000000..24cda90
--- /dev/null
+++ b/verilog/rtl/mprj_logic_high.v
@@ -0,0 +1,18 @@
+module mprj_logic_high (
+`ifdef USE_POWER_PINS
+    inout	   vccd1,
+    inout	   vssd1,
+`endif
+    output [458:0] HI
+);
+sky130_fd_sc_hd__conb_1 insts [458:0] (
+`ifdef USE_POWER_PINS
+                .VPWR(vccd1),
+                .VGND(vssd1),
+                .VPB(vccd1),
+                .VNB(vssd1),
+`endif
+                .HI(HI),
+                .LO()
+        );
+endmodule