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| /----------------------------------------------------------------------------\ |
| | | |
| | yosys -- Yosys Open SYnthesis Suite | |
| | | |
| | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> | |
| | | |
| | Permission to use, copy, modify, and/or distribute this software for any | |
| | purpose with or without fee is hereby granted, provided that the above | |
| | copyright notice and this permission notice appear in all copies. | |
| | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| | | |
| \----------------------------------------------------------------------------/ |
| |
| Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) |
| |
| [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. |
| |
| 1. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper_empty/../../verilog/rtl/defines.v |
| Parsing Verilog input from `/project/openlane/user_project_wrapper_empty/../../verilog/rtl/defines.v' to AST representation. |
| Successfully finished Verilog frontend. |
| |
| 2. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper_empty/../../verilog/rtl/user_proj_example.v |
| Parsing Verilog input from `/project/openlane/user_project_wrapper_empty/../../verilog/rtl/user_proj_example.v' to AST representation. |
| Generating RTLIL representation for module `\user_proj_example'. |
| Generating RTLIL representation for module `\counter'. |
| Successfully finished Verilog frontend. |
| |
| 3. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper_empty/../../verilog/rtl/defines.v |
| Parsing Verilog input from `/project/openlane/user_project_wrapper_empty/../../verilog/rtl/defines.v' to AST representation. |
| Successfully finished Verilog frontend. |
| |
| 4. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper_empty/../../verilog/rtl/user_project_wrapper.v |
| Parsing Verilog input from `/project/openlane/user_project_wrapper_empty/../../verilog/rtl/user_project_wrapper.v' to AST representation. |
| Generating RTLIL representation for module `\user_project_wrapper'. |
| /project/openlane/user_project_wrapper_empty/../../verilog/rtl/user_project_wrapper.v:68: Warning: Identifier `\vdda1' is implicitly declared. |
| /project/openlane/user_project_wrapper_empty/../../verilog/rtl/user_project_wrapper.v:69: Warning: Identifier `\vdda2' is implicitly declared. |
| /project/openlane/user_project_wrapper_empty/../../verilog/rtl/user_project_wrapper.v:70: Warning: Identifier `\vssa1' is implicitly declared. |
| /project/openlane/user_project_wrapper_empty/../../verilog/rtl/user_project_wrapper.v:71: Warning: Identifier `\vssa2' is implicitly declared. |
| /project/openlane/user_project_wrapper_empty/../../verilog/rtl/user_project_wrapper.v:72: Warning: Identifier `\vccd1' is implicitly declared. |
| /project/openlane/user_project_wrapper_empty/../../verilog/rtl/user_project_wrapper.v:73: Warning: Identifier `\vccd2' is implicitly declared. |
| /project/openlane/user_project_wrapper_empty/../../verilog/rtl/user_project_wrapper.v:74: Warning: Identifier `\vssd1' is implicitly declared. |
| /project/openlane/user_project_wrapper_empty/../../verilog/rtl/user_project_wrapper.v:75: Warning: Identifier `\vssd2' is implicitly declared. |
| Successfully finished Verilog frontend. |
| |
| 5. Generating Graphviz representation of design. |
| Writing dot description to `/project/openlane/user_project_wrapper_empty/runs/user_project_wrapper/tmp/synthesis/hierarchy.dot'. |
| Dumping module user_project_wrapper to page 1. |
| |
| 6. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 6.1. Analyzing design hierarchy.. |
| Top module: \user_project_wrapper |
| |
| 6.2. Analyzing design hierarchy.. |
| Top module: \user_project_wrapper |
| Removed 0 unused modules. |
| |
| 7. Printing statistics. |
| |
| === user_project_wrapper === |
| |
| Number of wires: 26 |
| Number of wire bits: 644 |
| Number of public wires: 26 |
| Number of public wire bits: 644 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 1 |
| user_proj_example 1 |
| |
| 8. Executing SPLITNETS pass (splitting up multi-bit signals). |
| |
| 9. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| |
| 10. Executing CHECK pass (checking for obvious problems). |
| checking module user_project_wrapper.. |
| found and reported 0 problems. |
| |
| 11. Printing statistics. |
| |
| === user_project_wrapper === |
| |
| Number of wires: 26 |
| Number of wire bits: 644 |
| Number of public wires: 26 |
| Number of public wire bits: 644 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 1 |
| user_proj_example 1 |
| |
| Area for cell type \user_proj_example is unknown! |
| |
| 12. Executing Verilog backend. |
| Dumping module `\user_project_wrapper'. |
| |
| Warnings: 8 unique messages, 8 total |
| End of script. Logfile hash: 313ab95b89, CPU: user 0.06s system 0.00s, MEM: 13.05 MB peak |
| Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) |
| Time spent: 64% 2x stat (0 sec), 17% 8x read_verilog (0 sec), ... |