| # SPDX-FileCopyrightText: 2020 Efabless Corporation |
| # |
| # Licensed under the Apache License, Version 2.0 (the "License"); |
| # you may not use this file except in compliance with the License. |
| # You may obtain a copy of the License at |
| # |
| # http://www.apache.org/licenses/LICENSE-2.0 |
| # |
| # Unless required by applicable law or agreed to in writing, software |
| # distributed under the License is distributed on an "AS IS" BASIS, |
| # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| # See the License for the specific language governing permissions and |
| # limitations under the License. |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| set script_dir [file dirname [file normalize [info script]]] |
| # User config |
| set ::env(DESIGN_NAME) DFFRAM |
| |
| # Change if needed |
| set ::env(VERILOG_FILES) "\ |
| $script_dir/../../verilog/rtl/defines.v\ |
| $script_dir/../../verilog/rtl/DFFRAM.v\ |
| $script_dir/../../verilog/rtl/DFFRAMBB.v" |
| |
| set ::env(SYNTH_TOP_LEVEL) 1 |
| set ::env(SYNTH_READ_BLACKBOX_LIB) 1 |
| # Fill this |
| set ::env(CLOCK_PERIOD) "10" |
| set ::env(CLOCK_PORT) "CLK" |
| set ::env(CLOCK_TREE_SYNTH) 0 |
| |
| set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg |
| |
| set ::env(FP_SIZING) absolute |
| set ::env(DIE_AREA) "0 0 750 525" |
| |
| set ::env(PDN_CFG) $script_dir/pdn.tcl |
| set ::env(GLB_RT_MAXLAYER) 5 |
| |
| set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0 |
| set ::env(PL_TARGET_DENSITY) 0.85 |
| |
| set ::env(CELL_PAD) 0 |
| set ::env(DIODE_INSERTION_STRATEGY) 0 |
