commit 370ca85d4d701db6f038ef72c018cff5629660f1
author Harrison Pham <harrison@harrisonpham.com> Sat Dec 19 01:51:25 2020 +0000
committer Harrison Pham <harrison@harrisonpham.com> Sat Dec 19 01:51:25 2020 +0000
tree 580b814ee14505355bfea394811a35f95df5fb69
parent 1fbeb643acab87de27efce607cbcd651d9a82ac2

Fix macro typo in tb

verilog/rtl/softshell/dv/softshell_top_tb.v

diff --git a/verilog/rtl/softshell/dv/softshell_top_tb.v b/verilog/rtl/softshell/dv/softshell_top_tb.v
index 5a7bdd1..b022a33 100644
--- a/verilog/rtl/softshell/dv/softshell_top_tb.v
+++ b/verilog/rtl/softshell/dv/softshell_top_tb.v
@@ -144,14 +144,14 @@
       read_assert(address + 4, ~data);
     end
     for (i = 0; i < `SHARED_MEM_WORDS * 4;
-         i = i + 4 * MEM_TEST_STEP_SIZE_WORDS) begin
+         i = i + 4 * `MEM_TEST_STEP_SIZE_WORDS) begin
       address = 32'h3000_0000 + i;
       data = i;
       write(address, data);
       read_assert(address, data);
     end
     for (i = 0; i < `SHARED_MEM_WORDS * 4;
-         i = i + 4 * MEM_TEST_STEP_SIZE_WORDS) begin
+         i = i + 4 * `MEM_TEST_STEP_SIZE_WORDS) begin
       address = 32'h3000_0000 + i;
       data = i;
       read_assert(address, data);