verilog/rtl/softshell/third_party/wb2axip/wb2axip.core

CAPI=1
[main]
description = Pipelined Wishbone to AXI converter

[fileset rtl]
files = rtl/wbm2axisp.v
file_type = verilogSource

[provider]
name=github
user=ZipCPU
repo=wb2axip
version = master