verilog/rtl/softshell/third_party/wb2axip/doc/gfx/wbxclk.json

{signal: [
  {name: 'i_reset',   wave: '1.0....................................................'},
  {name: 'i_wb_clk',  wave: '0.1010101.0101010.1010101.0101010.1010101.0101010.10101'},
  {name: 'i_wb_cyc',  wave: '0.....1.............................................0..'},
  {name: 'i_wb_stb',  wave: '0.....1.1..1.1.1..1.0.1.0..1.1.1..0....................'},
  {name: 'i_wb_addr', wave: '0.....3.4..5.6.7..8.0.9.0..3.4.5..0....................', data: ['A0','A1','A2','A3','A4','A5','A6','A7','A8','A9']},
  {name: 'o_wb_ack',  wave: '0..........................1.1.1..1.0.1.1..1.1.1..1.0..'},
  {name: 'o_wb_data', wave: '0..........................3.4.5..6.0.7.8..9.3.4..5.0..', data: ['D0','D1','D2','D3','D4','D5','D6','D7','D8','D9']},
  {},
  {name: 'i_xclk_clk',wave: '0.101.010.101.010.101.010.101.010.101.010.101.010.101.0'},
  {name: 'o_xclk_cyc',wave: '0.................1....................................'},
  {name: 'o_xclk_stb',wave: '0.................1.1..1..1.1..1..1.1..1..1.0..0..0.0..', data: ['D0','D1','D2','D3','d1','d2','d3','d4']},
  {name: 'i_xclk_ack',wave: '0.................1.1..1..1.1..1..1.1..1..1.0..0..0.0..', data: ['D0','D1','D2','D3','d1','d2','d3','d4']},
  {name: 'i_xclk_data',wave:'0.................3.4..5..6.7..8..9.3..4..5.0..0..0.0..', data: ['D0','D1','D2','D3','D4','D5','D6','D7','D8','D9']}
]}