verilog/rtl/softshell/third_party/wb2axip/doc/gfx/axivfifo.json

{signal: [
  {name: 'S_AXI_ARESETN', wave: '01......................................'},
  {name: 'S_AXI_ACLK',    wave: 'PP......................................'},
  {name: 'o_fill',        wave: '2..222222222222222222222................', data: ['0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16','17','18','19','20','21','22','23','24']},
  {name: 'o_empty',       wave: '1..0....................................'},
  {},
  {name: 'S_AXIS_TVALID', wave: '0.1.....................................'},
  {},
  {name: 'ififo_fill',    wave: '2..2.22222222...........................', data: ['0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16','17','18','19','20','21','22','23','24']},
  {name: 'M_AXI_AWVALID', wave: '0...........10......10......10......10..'},
  {name: 'M_AXI_WVALID',  wave: '0...........2345678923456789234567892345'},
  {name: 'M_AXI_WLAST',   wave: 'x...........0......10......10......10...', data: ['A0','A1','A2','A3','A4','A5','A6','A7','A8','A9']},
  {name: 'M_AXI_BVALID',  wave: '0...................10......10......10..'},
  {},
  {name: 'M_AXI_ARVALID',wave: '0....................10......10......10.'},
  {name: 'M_AXI_RVALID', wave: '0.....................23456789234567890.'},
  {name: 'M_AXI_RLAST',  wave: 'x.....................0......10......1x.', data: ['D0','D1','D2','D3','d1','d2','d3','d4']},
  {},
  {name: 'ofifo_fill',  wave:  '0......................2...............0', data: ['1']},
  {name: 'M_AXI_TVALID',wave:  '0......................11111111111111110', data: ['D0','D1','D2','D3','d1','d2','d3','d4']},
]}