verilog/rtl/softshell/third_party/wb2axip/doc/gfx/axivdma.json

{signal: [
  {name: 'ACLK',       wave: 'P..........................................'},
  {name: 'ARESETN',    wave: '01.........................................'},
  {},
  {name: 'cfg_active', wave: '0....1.....................................'},
  {},
  {name: 'M_AXI_ARVALID', wave: '0........10.10.10.10.10.10.10.10.10.10.10.1'},
  {name: 'M_AXI_ARADDR',  wave: '0........3..4..5..6..7..8..9..3..4..5..6..7'},
  {name: 'M_AXI_ARLEN',   wave: 'x........2.................................', data: ['5']},
  {},
  {name: 'M_AXI_RVALID', wave: '0.........1........................01....01'},
  {name: 'M_AXI_RDATA',  wave: 'x.........3333334444445555556666667x77777x8'},
  {name: 'M_AXI_RLAST',  wave: 'x.........0....30....40....50....60x0...7x0'},
  {},
  {name: 'M_AXIS_TVALID', wave: '0..........1........................01....0'},
  {name: 'M_AXIS_TDATA',  wave: 'x..........3333334444445555556666667x77777x'},
  {name: 'H-LAST',        wave: 'x..........0....10....10....10....10.....1x'},
  {name: 'V-LAST',        wave: 'x..........0.............................1x'},
]}